{"title":"A 256 Meg SDRAM BIST for disturb test application","authors":"T. Powell, D. Cline, F. Hii","doi":"10.1109/TEST.1997.639614","DOIUrl":null,"url":null,"abstract":"The Disturb Test Algorithms are targeted for row adjacent coupled defects that can be time elapsed dependent. A BIST design is described for application of these tests for testing 256 Meg SDRAM chips.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"68 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings International Test Conference 1997","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/TEST.1997.639614","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 6
Abstract
The Disturb Test Algorithms are targeted for row adjacent coupled defects that can be time elapsed dependent. A BIST design is described for application of these tests for testing 256 Meg SDRAM chips.
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