{"title":"一种在线自检开关电流积分器","authors":"Osama K. Abu-Shahla, I. Bell","doi":"10.1109/TEST.1997.639652","DOIUrl":null,"url":null,"abstract":"We describe a CMOS on-line-self-testing, double-sampled, fully-balanced, switched-current bilinear integrator. High spot-defect fault coverage of the integrator, clock generator and checking circuit is achieved under normal process variations.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"9 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"An on-line self-testing switched-current integrator\",\"authors\":\"Osama K. Abu-Shahla, I. Bell\",\"doi\":\"10.1109/TEST.1997.639652\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We describe a CMOS on-line-self-testing, double-sampled, fully-balanced, switched-current bilinear integrator. High spot-defect fault coverage of the integrator, clock generator and checking circuit is achieved under normal process variations.\",\"PeriodicalId\":186340,\"journal\":{\"name\":\"Proceedings International Test Conference 1997\",\"volume\":\"9 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1997-11-03\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings International Test Conference 1997\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/TEST.1997.639652\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings International Test Conference 1997","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/TEST.1997.639652","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An on-line self-testing switched-current integrator
We describe a CMOS on-line-self-testing, double-sampled, fully-balanced, switched-current bilinear integrator. High spot-defect fault coverage of the integrator, clock generator and checking circuit is achieved under normal process variations.
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