{"title":"AMD-K6/sup TM/微处理器的可测试性特点","authors":"R. S. Fetherston, I. Shaik, Siyad C. Ma","doi":"10.1109/TEST.1997.639643","DOIUrl":null,"url":null,"abstract":"This paper describes the testability features and test pattern development methodologies for the AMD-K6/sup TM/ microprocessor. The embedded design for testability (DFT) structures and test strategy provide high quality manufacturing tests.","PeriodicalId":186340,"journal":{"name":"Proceedings International Test Conference 1997","volume":"13 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"22","resultStr":"{\"title\":\"Testability features of AMD-K6/sup TM/ microprocessor\",\"authors\":\"R. S. Fetherston, I. Shaik, Siyad C. Ma\",\"doi\":\"10.1109/TEST.1997.639643\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper describes the testability features and test pattern development methodologies for the AMD-K6/sup TM/ microprocessor. The embedded design for testability (DFT) structures and test strategy provide high quality manufacturing tests.\",\"PeriodicalId\":186340,\"journal\":{\"name\":\"Proceedings International Test Conference 1997\",\"volume\":\"13 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1997-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"22\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings International Test Conference 1997\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/TEST.1997.639643\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings International Test Conference 1997","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/TEST.1997.639643","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Testability features of AMD-K6/sup TM/ microprocessor
This paper describes the testability features and test pattern development methodologies for the AMD-K6/sup TM/ microprocessor. The embedded design for testability (DFT) structures and test strategy provide high quality manufacturing tests.
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