The case for partial scan

Abstract

The full scan design methodology undisputably has many benefits throughout the process of ASIC and system design and during the life cycle of a product that may justify its use, but it has some very definite costs as well. These include larger die area, reduced circuit performance and the fact that there are usually a number of memory elements which are not scanned. It is suggested that partial scan be useful in augmenting the test coverage on critical portions of high performance chips, and that it can also serve as the basis for an area-efficient design methodology on any chip. Partial scan is another facet of the continual improvement process in IC design. As new developments in flip-flop selection and sequential ATPG are integrated into design flows, partial scan can become as push-button as full scan now is. When coupled with a design methodology driven by timing analysis and synthesis, partial scan could well be the key to producing designs that are optimized for performance, area, and testability.