2010 IEEE Electrical Design of Advanced Package & Systems Symposium最新文献_第3页

Area-I/O RDL routing for chip-package codesign considering regional assignment 考虑区域分配的芯片封装协同设计的区域i /O RDL路由

2010 IEEE Electrical Design of Advanced Package & Systems Symposium Pub Date : 2010-12-01 DOI: 10.1109/EDAPS.2010.5683021

Kun-Sheng Lin, H. Hsu, R. Lee, Hung-Ming Chen

引用次数: 8

Noise improvement of 3–5GHz CMOS UWB LNA 3-5GHz CMOS超宽带LNA的噪声改进

2010 IEEE Electrical Design of Advanced Package & Systems Symposium Pub Date : 2010-12-01 DOI: 10.1109/EDAPS.2010.5683009

Chia-Chien Li, Yi-Chen Chen, Jeng-Rern Yang

引用次数: 2

A simple & cost-effective novel methodology for predicting SSN system performance for different PCB trace lengths 预测不同PCB走线长度的SSN系统性能的一种简单且经济有效的新方法

2010 IEEE Electrical Design of Advanced Package & Systems Symposium Pub Date : 2010-12-01 DOI: 10.1109/EDAPS.2010.5683031

C. Ang, Wei Wei Lo, M. Wong

{"title":"A simple & cost-effective novel methodology for predicting SSN system performance for different PCB trace lengths","authors":"C. Ang, Wei Wei Lo, M. Wong","doi":"10.1109/EDAPS.2010.5683031","DOIUrl":"https://doi.org/10.1109/EDAPS.2010.5683031","url":null,"abstract":"High data rates, high clock speeds, and low power consumption are synonymous with advanced electronic devices. Consequently, simultaneous switching noise (SSN) is emerging as a critical side-effect of toggling signals within an electronic device because SSN affects signal integrity. Even minute changes in signal voltage in the order of a few millivolts can adversely affect the functioning of a circuit. A PCB typically forms the communication backbone between electronic components including field programmable gate array (FPGA) devices. Signal quality and SSN effects vary with PCB trace lengths. Traditionally, complex board models are used to simulate the SSN characteristics of electronic devices for different PCBs, which can be time consuming and expensive. This paper presents a cost-effective novel methodology for de-embedding the PCB trace effect to accurately characterize an FPGA device's intrinsic SSN characteristics. The methodology uses simple and fast measurement and simulation techniques to de-embed the PCB trace effect for different PCB trace lengths. The predicted SSN data for different PCB trace lengths and intrinsic SSN data obtained using this methodology will be useful to FPGA system designers.","PeriodicalId":185326,"journal":{"name":"2010 IEEE Electrical Design of Advanced Package & Systems Symposium","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134315347","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

A dual-band filter using stepped-impedance resonator (SIR) embedded into substrate integrated waveguide (SIW) 基于阶跃阻抗谐振器(SIR)嵌入衬底集成波导(SIW)的双带滤波器

2010 IEEE Electrical Design of Advanced Package & Systems Symposium Pub Date : 2010-12-01 DOI: 10.1109/EDAPS.2010.5683025

Linsheng Wu, J. Mao, W. Yin, Yong-xin Guo

引用次数: 22

Origins of electromagnetic immunity holes of microcontrollers 微控制器电磁抗扰孔的起源

2010 IEEE Electrical Design of Advanced Package & Systems Symposium Pub Date : 2010-12-01 DOI: 10.1109/EDAPS.2010.5683027

Tao Su, T. Steinecke, M. Unger

引用次数: 0

Electrothermal modeling of coaxial through silicon via (TSV) for three-dimensional ICs 三维集成电路同轴硅通孔(TSV)的电热模拟

2010 IEEE Electrical Design of Advanced Package & Systems Symposium Pub Date : 2010-12-01 DOI: 10.1109/EDAPS.2010.5683012

Wensheng Zhao, Xiao-Peng Wang, Xiao-Long Xu, W. Yin

引用次数: 7

On-chip PDN design effects on 3D stacked on-chip PDN impedance based on TSV interconnection 片上PDN设计对基于TSV互连的三维堆叠片上PDN阻抗的影响

2010 IEEE Electrical Design of Advanced Package & Systems Symposium Pub Date : 2010-12-01 DOI: 10.1109/EDAPS.2010.5682994

J. Pak, Joohee Kim, Jonghyun Cho, Junho Lee, Hyungdong Lee, Kunwoo Park, Joungho Kim

{"title":"On-chip PDN design effects on 3D stacked on-chip PDN impedance based on TSV interconnection","authors":"J. Pak, Joohee Kim, Jonghyun Cho, Junho Lee, Hyungdong Lee, Kunwoo Park, Joungho Kim","doi":"10.1109/EDAPS.2010.5682994","DOIUrl":"https://doi.org/10.1109/EDAPS.2010.5682994","url":null,"abstract":"This paper presents the analyses of 3D (3 Dimensional) stacked on-chip PDN (Power Distribution Network) impedances, which are composed with on-chip PDNs and TSV (Through Silicon Via) interconnections, and show the various features depending on on-chip PDN designs and 3D stacked chip configurations. Multi-stacked on-chip PDNs with very large capacitances interacting with even very small inductive TSV interconnections induces high PDN impedance peaks in GHz range, where single chip-PDN shows low PDN impedance. As multi-stacked on-chip PDN has larger capacitance, the high PDN impedance peaks appear at lower frequency range due to the relation of on-chip PDN capacitance and TSV inductance. Therefore, analysis and evaluation of on-chip PDN are very important to design 3D stacked chip. First, PDN impedance of single meshed type on-chip PDN is evaluated by the proposed on-chip PDN model and the measurement. Second, by using the evaluated on-chip PDN impedances and simple inductor model of TSV, the PDN impedances of 3D stacked on-chip PDNs is analyzed in consideration with the various on-chip PDN designs and stacked on-chip PDN numbers.","PeriodicalId":185326,"journal":{"name":"2010 IEEE Electrical Design of Advanced Package & Systems Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128630258","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

Wideband transitions for wafer level MEMS packages 用于晶圆级MEMS封装的宽带转换

2010 IEEE Electrical Design of Advanced Package & Systems Symposium Pub Date : 2010-12-01 DOI: 10.1109/EDAPS.2010.5683016

Y. Lim, A. Yu, Bangtao Chen

引用次数: 0

Design of toroidal current probe embedded in multi-layer printed circuit boards for electrostatic discharge(ESD) detection 用于静电放电检测的多层印刷电路板环形电流探头设计

2010 IEEE Electrical Design of Advanced Package & Systems Symposium Pub Date : 2010-12-01 DOI: 10.1109/EDAPS.2010.5682996

Hajin Sung, Eakhwan Song, M. Kim, Yujeong Shim, Sunkyu Kong, J. Kwon, Joungho Kim

引用次数: 1

Design and simulation of a compact novel LTCC antenna for integrated Bluetooth applications 用于集成蓝牙应用的小型新型LTCC天线的设计与仿真

2010 IEEE Electrical Design of Advanced Package & Systems Symposium Pub Date : 2010-12-01 DOI: 10.1109/EDAPS.2010.5682995

Hu Ji-gang, J. Long, Jiang Wan-bing, Yang Shi-zhao

引用次数: 7