Area-I/O RDL routing for chip-package codesign considering regional assignment

Abstract

Flip-Chip package provides high density I/Os and better performance in package size, signal/power integrety, and wirelength. Routing on its Re-Distribution Layer (RDL) is one of the most difficult stage in Flip-Chip packaging due to the increasing number of I/Os in modern VLSI designs. Area I/O can shorten the signal path and further increases the I/O density, but the design complexity is also higher. The Area I/O RDL routing problem is introduced in this paper, considering wirelength minimization and chip-package codesign. The proposed algorithm effectively solves the problem. 100% routability is guaranteed, from block ports to I/O pads and from I/O pads to bump pads. The authors propose the concept of regional assignment to evaluate the skew between bumps and balls. It leads the nets to route within neighbor sectors rather than the opposite sector. The experimental results, on 7 industrial designs, show that the router greatly minimizes bump-ball skew compared with [12], with reasonable extra wirelength.