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2010 IEEE Electrical Design of Advanced Package & Systems Symposium最新文献

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Effective interconnect networks design in CMOS 45 nm circuits to joint reductions of XT and delay for transmission of very high speed signals 在CMOS 45纳米电路中设计有效的互连网络，以联合降低XT和传输非常高速信号的延迟
2010 IEEE Electrical Design of Advanced Package & Systems Symposium Pub Date : 2010-12-16 DOI: 10.1109/EDAPS.2010.5683042
S. D. Rivaz, Alexis Farcy, Denis Deschacht, Thierry Lacrevaz, Bernard, Flechet
{"title":"Effective interconnect networks design in CMOS 45 nm circuits to joint reductions of XT and delay for transmission of very high speed signals","authors":"S. D. Rivaz, Alexis Farcy, Denis Deschacht, Thierry Lacrevaz, Bernard, Flechet","doi":"10.1109/EDAPS.2010.5683042","DOIUrl":"https://doi.org/10.1109/EDAPS.2010.5683042","url":null,"abstract":"When high speed integrated digital circuits technology scales down from one node to the other as ITRS recommends, a significant gain is obtained on signal speed, consumption and area of CMOS transistors. Nevertheless a specific issue occurs from the 45 nm technology node. The obtained gain on active devices is foiled by an increase of interconnect propagation delays and critical crosstalk (XT) levels in the Back-End of Line (BEOL). This issue especially concerns relatively long (few hundred of μm) interconnects of the intermediate metal level. By introducing drivers (repeaters) in order to divide long interconnect in shorter sections and choosing optimal drivers sizes, speed can be maximized as well as crosstalk levels are alleviated. The present studies aims at specify couple of intervals for both section lengths and drivers size in accordance with speed and crosstalk levels requirements of future ICs. When it becomes hard to meet all requirements, it is shown that the interconnect density constraint should be relaxed.","PeriodicalId":185326,"journal":{"name":"2010 IEEE Electrical Design of Advanced Package & Systems Symposium","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133810072","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Concurrent analysis of self-heating effect and thermal stress in partially insulated field effect transistors (PiFETs) 部分绝缘场效应晶体管(pifet)自热效应和热应力的并行分析
2010 IEEE Electrical Design of Advanced Package & Systems Symposium Pub Date : 2010-12-01 DOI: 10.1109/EDAPS.2010.5683047
Ming-Guang Yi, W. Yin
{"title":"Concurrent analysis of self-heating effect and thermal stress in partially insulated field effect transistors (PiFETs)","authors":"Ming-Guang Yi, W. Yin","doi":"10.1109/EDAPS.2010.5683047","DOIUrl":"https://doi.org/10.1109/EDAPS.2010.5683047","url":null,"abstract":"A coupled electro-thermal-mechanical analysis of partially insulated field-effect transistors (PiFETs) is performed using the proposed hybrid nonlinear finite element method (FEM) with temperature-dependent parameters rigorously treated. The two major structures of PiFET, namely the partially insulating oxide (PiOX) under the drain and source (PUSD) and partially insulating oxide under the channel (PUC) structures are thoroughly studied. For comparison, the normal MOSFET and SOI FET are also investigated. The study of self-heating effect (SHE) in these devices indicates that the PiFET is more thermally efficient than conventional SOI device. Moreover, to fully investigate the SHE and SHE induce thermal stress, different choices of parameters related to PiOX are further studied and discussed.","PeriodicalId":185326,"journal":{"name":"2010 IEEE Electrical Design of Advanced Package & Systems Symposium","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115307989","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Controllable slow-wave delay line 可控慢波延迟线
2010 IEEE Electrical Design of Advanced Package & Systems Symposium Pub Date : 2010-12-01 DOI: 10.1109/EDAPS.2010.5683013
Jinglin Shi, Y. Xiong, Sanming Hu, Lei Wang, Bolun Zhang
{"title":"Controllable slow-wave delay line","authors":"Jinglin Shi, Y. Xiong, Sanming Hu, Lei Wang, Bolun Zhang","doi":"10.1109/EDAPS.2010.5683013","DOIUrl":"https://doi.org/10.1109/EDAPS.2010.5683013","url":null,"abstract":"On-chip transmission lines are basic components in millimeter-wave and terahertz circuits. In this paper, slow-wave CPW with a simple mosfet switch, ie. controllable slow-wave CPW as a controllable phase delay line are designed, characterized and analyzed in a commercial 0.18μm CMOS process. Based on measured two-port S-parameters up to 110GHz, the phase constants are compared at variation of the bias. It shows a continuously 15° delay over frequency range of 63 GHz to 98 GHz with a minimum insertion loss of 3.2 dB and a maximum insertion loss of 5.5 dB.","PeriodicalId":185326,"journal":{"name":"2010 IEEE Electrical Design of Advanced Package & Systems Symposium","volume":"39 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116416282","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Package design for high-speed SerDes 高速伺服器的封装设计
2010 IEEE Electrical Design of Advanced Package & Systems Symposium Pub Date : 2010-12-01 DOI: 10.1109/EDAPS.2010.5682990
B. Young, A. Bhandal
{"title":"Package design for high-speed SerDes","authors":"B. Young, A. Bhandal","doi":"10.1109/EDAPS.2010.5682990","DOIUrl":"https://doi.org/10.1109/EDAPS.2010.5682990","url":null,"abstract":"High-speed SerDes signals are significantly distorted by the time they leave the package. The distortion is caused by excess capacitive loading at points along the signal path, causing reflections. The reflections can be minimized through design modifications, added structures for compensation, filters, and characteristic impedance shifts.","PeriodicalId":185326,"journal":{"name":"2010 IEEE Electrical Design of Advanced Package & Systems Symposium","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129873236","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Recent development of via models: Hybrid circuit and field analysis 通孔模型的最新发展:混合电路和现场分析
2010 IEEE Electrical Design of Advanced Package & Systems Symposium Pub Date : 2010-12-01 DOI: 10.1109/EDAPS.2010.5683001
Yaojiang Zhang, J. Fan
{"title":"Recent development of via models: Hybrid circuit and field analysis","authors":"Yaojiang Zhang, J. Fan","doi":"10.1109/EDAPS.2010.5683001","DOIUrl":"https://doi.org/10.1109/EDAPS.2010.5683001","url":null,"abstract":"Via-plate interaction can be modeled as lumped circuits for vias and a two-dimensional field problem for the plate domain. The accuracy of the improved intrinsic via model and the conventional physics-based via model is investigated by comparing them with either analytical formula or numerical simulations for a via in a circular plate pair with various edge boundary conditions. It is found that the intrinsic via model matches very well with both the analytical formula and numerical solutions in all the examples studied. However, the physics-based via model is only an acceptable approximation at low frequencies and its accuracy is not dependent on the plate size but on the via itself. It is observed that the physics-based via model is more accurate for a plate par with smaller plate separations.","PeriodicalId":185326,"journal":{"name":"2010 IEEE Electrical Design of Advanced Package & Systems Symposium","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123975390","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Electrothermal investigation on through silicon multi-walled carbon nanotube via interconnects 通硅多壁碳纳米管的电热特性研究
2010 IEEE Electrical Design of Advanced Package & Systems Symposium Pub Date : 2010-12-01 DOI: 10.1109/EDAPS.2010.5682991
Jiang-Peng Cui, Xiao-Long Xu, W. Yin
{"title":"Electrothermal investigation on through silicon multi-walled carbon nanotube via interconnects","authors":"Jiang-Peng Cui, Xiao-Long Xu, W. Yin","doi":"10.1109/EDAPS.2010.5682991","DOIUrl":"https://doi.org/10.1109/EDAPS.2010.5682991","url":null,"abstract":"This paper presents hybrid analysis of through silicon multi-walled carbon nanotube vias. A set of equivalent lumped-element circuit models for two through silicon multi-walled carbon nanotube via (TS-MWCNTV) interconnects are proposed, with quantum effect treated appropriately. The methods for characterizing all frequency- and temperature-dependent RLCG parameters of a couple of TS-MWCNTVs are then given, including their effective capacitance, effective conductance, and characteristic impedance. Further, hybrid effects of frequency, as well as temperature on the conductance of open structure is examined. Also, the time delay of the TS-MWCNTV is studied.","PeriodicalId":185326,"journal":{"name":"2010 IEEE Electrical Design of Advanced Package & Systems Symposium","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124051564","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Wideband bandpass filter design for D-band application d波段应用的宽带带通滤波器设计
2010 IEEE Electrical Design of Advanced Package & Systems Symposium Pub Date : 2010-12-01 DOI: 10.1109/EDAPS.2010.5683038
Rui Li, T. Lim, S. W. Ho, Y. Xiong, Y. Khoo
{"title":"Wideband bandpass filter design for D-band application","authors":"Rui Li, T. Lim, S. W. Ho, Y. Xiong, Y. Khoo","doi":"10.1109/EDAPS.2010.5683038","DOIUrl":"https://doi.org/10.1109/EDAPS.2010.5683038","url":null,"abstract":"This paper presents the design and characterization of a wideband bandpass filter for millimetre-wave D-band application. The filter is implemented on a three-layer thin film structure using benzocyclobutene (BCB) silicon technology. Two stepped-impedance resonators are used to construct the bandpass filter, while the input/output coupling is achieved by coplanar waveguide (CPW) to stripline transition. The prototype filter is fabricated and measured. The measurement results agree with the simulation results well and exhibit a wideband bandpass filtering response with fractional bandwidth of 32.2% at 135.6 GHz. The mid-band insertion loss is only 2.94 dB.","PeriodicalId":185326,"journal":{"name":"2010 IEEE Electrical Design of Advanced Package & Systems Symposium","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127769438","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Study of high speed interconnects of multiple dies stack structure with Through-Silicon-Via (TSV) 通硅孔(TSV)多晶片堆叠结构高速互连研究
2010 IEEE Electrical Design of Advanced Package & Systems Symposium Pub Date : 2010-12-01 DOI: 10.1109/EDAPS.2010.5683014
Zhang Wenle, Khoo Yee Mong, Lim Teck Guan, P. Damaruganath, Teo Keng Hwa, Zhang Xiaowu
{"title":"Study of high speed interconnects of multiple dies stack structure with Through-Silicon-Via (TSV)","authors":"Zhang Wenle, Khoo Yee Mong, Lim Teck Guan, P. Damaruganath, Teo Keng Hwa, Zhang Xiaowu","doi":"10.1109/EDAPS.2010.5683014","DOIUrl":"https://doi.org/10.1109/EDAPS.2010.5683014","url":null,"abstract":"Die stacking is widely adopted for high chip count systems to reduce the requirement of substrate area. The incorporation of Through-Silicon-Via (TSV) as vertical interconnects further reduces the interconnect path length from the top die to substrate. As the fabrication resolution keeps on shrinking, devices of even higher chip count are required to be assembled in a single package, which results in even longer 3D interconnects. As such, accurate modelling of high speed interconnects is essential for the high frequency systems. In this work, 3D modelling and Full wave EM simulation were performed on the interconnect path which consists of TSV, metal re-distribution Layer (RDL) and bumps. Effect of the different number of die stack was analyzed based on the simulation results.","PeriodicalId":185326,"journal":{"name":"2010 IEEE Electrical Design of Advanced Package & Systems Symposium","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134559367","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 60 GHz flip-chip bandpass filter in standard CMOS technology 标准CMOS技术中的60 GHz倒装带通滤波器
2010 IEEE Electrical Design of Advanced Package & Systems Symposium Pub Date : 2010-12-01 DOI: 10.1109/EDAPS.2010.5683033
Debin Hou, Y. Xiong, Y. Lim, W. Goh, Jiankang Li, T. Lim, W. Hong
{"title":"A 60 GHz flip-chip bandpass filter in standard CMOS technology","authors":"Debin Hou, Y. Xiong, Y. Lim, W. Goh, Jiankang Li, T. Lim, W. Hong","doi":"10.1109/EDAPS.2010.5683033","DOIUrl":"https://doi.org/10.1109/EDAPS.2010.5683033","url":null,"abstract":"In this paper, a novel 60 GHz flip-chip bandpass filter in standard CMOS technology is proposed. An insertion loss of 0.69 dB/mm for microstrip line is obtained at 60 GHz by using cascaded THRU de-embedding method. By deploying the gap between the flip-chip bump and the flipped chip, an endcoupled, half-wavelength resonator filter is designed and fabricated. The measured insertion loss of 3.3 dB and return loss of >13 dB with a bandwidth of 63% at centre frequency of 60 GHz clearly demonstrates that the proposed flip-chip filter is a promising candidate for 60 GHz integrated circuits applications.","PeriodicalId":185326,"journal":{"name":"2010 IEEE Electrical Design of Advanced Package & Systems Symposium","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127649689","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A new methodology for IC-package thermal co-analysis in 3D IC environment 三维集成电路环境下集成电路封装热协同分析的新方法
2010 IEEE Electrical Design of Advanced Package & Systems Symposium Pub Date : 2010-12-01 DOI: 10.1115/IPACK2011-52240
S. Pan, N. Chang, Ji Zheng
{"title":"A new methodology for IC-package thermal co-analysis in 3D IC environment","authors":"S. Pan, N. Chang, Ji Zheng","doi":"10.1115/IPACK2011-52240","DOIUrl":"https://doi.org/10.1115/IPACK2011-52240","url":null,"abstract":"Power on chip is highly temperature dependent in deep sub-micron VLSI. With increasing power density in modern 3D-IC and SiP, thermal induced reliability and performance issues such as leakage power and electromigration must be taken into consideration in the system level design. This paper presents a new methodology to accurately and efficiently predict power and temperature distribution for 3D ICs.","PeriodicalId":185326,"journal":{"name":"2010 IEEE Electrical Design of Advanced Package & Systems Symposium","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115600297","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
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