{"title":"三维集成电路环境下集成电路封装热协同分析的新方法","authors":"S. Pan, N. Chang, Ji Zheng","doi":"10.1115/IPACK2011-52240","DOIUrl":null,"url":null,"abstract":"Power on chip is highly temperature dependent in deep sub-micron VLSI. With increasing power density in modern 3D-IC and SiP, thermal induced reliability and performance issues such as leakage power and electromigration must be taken into consideration in the system level design. This paper presents a new methodology to accurately and efficiently predict power and temperature distribution for 3D ICs.","PeriodicalId":185326,"journal":{"name":"2010 IEEE Electrical Design of Advanced Package & Systems Symposium","volume":"102 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":"{\"title\":\"A new methodology for IC-package thermal co-analysis in 3D IC environment\",\"authors\":\"S. Pan, N. Chang, Ji Zheng\",\"doi\":\"10.1115/IPACK2011-52240\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Power on chip is highly temperature dependent in deep sub-micron VLSI. With increasing power density in modern 3D-IC and SiP, thermal induced reliability and performance issues such as leakage power and electromigration must be taken into consideration in the system level design. This paper presents a new methodology to accurately and efficiently predict power and temperature distribution for 3D ICs.\",\"PeriodicalId\":185326,\"journal\":{\"name\":\"2010 IEEE Electrical Design of Advanced Package & Systems Symposium\",\"volume\":\"102 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2010-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"9\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2010 IEEE Electrical Design of Advanced Package & Systems Symposium\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1115/IPACK2011-52240\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 IEEE Electrical Design of Advanced Package & Systems Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1115/IPACK2011-52240","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A new methodology for IC-package thermal co-analysis in 3D IC environment
Power on chip is highly temperature dependent in deep sub-micron VLSI. With increasing power density in modern 3D-IC and SiP, thermal induced reliability and performance issues such as leakage power and electromigration must be taken into consideration in the system level design. This paper presents a new methodology to accurately and efficiently predict power and temperature distribution for 3D ICs.
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