Controllable slow-wave delay line

Jinglin Shi, Y. Xiong, Sanming Hu, Lei Wang, Bolun Zhang
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引用次数: 3

Abstract

On-chip transmission lines are basic components in millimeter-wave and terahertz circuits. In this paper, slow-wave CPW with a simple mosfet switch, ie. controllable slow-wave CPW as a controllable phase delay line are designed, characterized and analyzed in a commercial 0.18μm CMOS process. Based on measured two-port S-parameters up to 110GHz, the phase constants are compared at variation of the bias. It shows a continuously 15° delay over frequency range of 63 GHz to 98 GHz with a minimum insertion loss of 3.2 dB and a maximum insertion loss of 5.5 dB.
可控慢波延迟线
片上传输线是毫米波和太赫兹电路的基本组成部分。在本文中,慢波CPW与一个简单的大多数场效应晶体管开关,即。在商用0.18μm CMOS工艺上设计了可控慢波CPW作为可控相位延迟线,并对其进行了表征和分析。基于测量到的110GHz双端口s参数,比较了在偏置变化下的相位常数。它在63 GHz至98 GHz的频率范围内显示连续15°延迟,最小插入损耗为3.2 dB,最大插入损耗为5.5 dB。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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