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2010 IEEE Electrical Design of Advanced Package & Systems Symposium最新文献

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A tri-band filter using tri-mode stub-loaded resonators (SLRs) 一种使用三模桩负载谐振器(slr)的三带滤波器
2010 IEEE Electrical Design of Advanced Package & Systems Symposium Pub Date : 2010-12-01 DOI: 10.1109/EDAPS.2010.5683032
Q. Yin, Linsheng Wu, Liang Zhou, W. Yin
{"title":"A tri-band filter using tri-mode stub-loaded resonators (SLRs)","authors":"Q. Yin, Linsheng Wu, Liang Zhou, W. Yin","doi":"10.1109/EDAPS.2010.5683032","DOIUrl":"https://doi.org/10.1109/EDAPS.2010.5683032","url":null,"abstract":"The tri-mode stub-loaded resonators (SLRs) are employed in the design of a tri-band bandpass filter (BPF), where a special coupling structure is used to provide enough design freedom, and a magnetic source-load coupling is introduced to improve the frequency selectivity with six transmission zeros. The good performance of our proposed filter is demonstrated by good agreement obtained between the simulated and measured S-parameters.","PeriodicalId":185326,"journal":{"name":"2010 IEEE Electrical Design of Advanced Package & Systems Symposium","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116544815","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Performance enhancement of degenerated antenna system due to external digital circuits 外部数字电路对退化天线系统性能的增强
2010 IEEE Electrical Design of Advanced Package & Systems Symposium Pub Date : 2010-12-01 DOI: 10.1109/EDAPS.2010.5683005
Hee-Do Kang, Tong-Ho Chung, Chang-Han Jun, J. Yook
{"title":"Performance enhancement of degenerated antenna system due to external digital circuits","authors":"Hee-Do Kang, Tong-Ho Chung, Chang-Han Jun, J. Yook","doi":"10.1109/EDAPS.2010.5683005","DOIUrl":"https://doi.org/10.1109/EDAPS.2010.5683005","url":null,"abstract":"In this paper, performance of the antenna system is analyzed, as the clock frequency in the external digital circuit is increased. To verify the interrelation between antenna performance and digital clock, inverted-F antenna system and the mixed signal circuit are designed. Besides, the coupled noises to the antenna system are analyzed as the operating frequency of the digital clock is increased by 0.5, 1, and 2 GHz. Hence, the peak to peak coupled noises to the antenna system are 1.169, 3.386, and 18.034 mV for periodic digital clocks, and 2.054, 6.316, and 17.379 mV for random digital clocks, respectively. Therefore, to reduce the coupled noise to the antenna system due to the digital clocks, several methods are proposed; anti-resonance structure, 180° delay line, and LC filter. As a result, maximum ratio of the noise reduction is achieved about 78% by applying 180° delay line.","PeriodicalId":185326,"journal":{"name":"2010 IEEE Electrical Design of Advanced Package & Systems Symposium","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133942224","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A low-cost high-gain antenna array and its integration with active circuits 一种低成本高增益天线阵列及其与有源电路的集成
2010 IEEE Electrical Design of Advanced Package & Systems Symposium Pub Date : 2010-12-01 DOI: 10.1109/EDAPS.2010.5683020
Sanming Hu, Y. Xiong, Lei Wang, Debin Hou, T. Lim
{"title":"A low-cost high-gain antenna array and its integration with active circuits","authors":"Sanming Hu, Y. Xiong, Lei Wang, Debin Hou, T. Lim","doi":"10.1109/EDAPS.2010.5683020","DOIUrl":"https://doi.org/10.1109/EDAPS.2010.5683020","url":null,"abstract":"At millimeter-wave frequencies, high-gain antenna and its integration with active circuits are of great concern. In this paper, a 2×4 antenna array is designed and fabricated on printed circuit board (PCB). At 135 GHz, the maximum gain is 15.4 dBi. It is much higher than that of a conventional on-chip antenna which is usually lower than −10 dBi. Subsequently, the low-cost wire-bonding technology is studied and adopted to integrate this array with active circuits.","PeriodicalId":185326,"journal":{"name":"2010 IEEE Electrical Design of Advanced Package & Systems Symposium","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132488202","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Advanced model order reduction technique in real-life IC/package design 在实际IC/封装设计中先进的模型降阶技术
2010 IEEE Electrical Design of Advanced Package & Systems Symposium Pub Date : 2010-12-01 DOI: 10.1109/EDAPS.2010.5683000
Z. Peng, Yang Shao, Jin-Fa Lee
{"title":"Advanced model order reduction technique in real-life IC/package design","authors":"Z. Peng, Yang Shao, Jin-Fa Lee","doi":"10.1109/EDAPS.2010.5683000","DOIUrl":"https://doi.org/10.1109/EDAPS.2010.5683000","url":null,"abstract":"An real-life packaging is a multi-port system with a wide band frequency of interest. The efficient solution of such multi-input/multi-output responses over a wide frequency band adds extraordinary computational complexity to Electromagnetic simulation. In this paper, we proposed an advance model order reduction (MOR) algorithm, that is capable of producing fast and accurate computation of multi-port multi-frequency responses. This MOR technique is based on a multipoint Galerkin asymptotic waveform evaluation (MGAWE) to automate the fast frequency sweep process, and a recycling Krylov subspaces method, GCRO-DR, to gain further efficiency and to reduce the needed matrix-vector (MV) multiplications required in solving DDM matrix equation at different frequencies with multi-port excitation. Numerical results verify the analysis and demonstrate the effectiveness of the proposed method on a real-life 3-D full package signal integrity analysis.","PeriodicalId":185326,"journal":{"name":"2010 IEEE Electrical Design of Advanced Package & Systems Symposium","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125011618","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Chip-package-board co-design for complex System-on-Chip (SoC) 复杂片上系统(SoC)的芯片封装板协同设计
2010 IEEE Electrical Design of Advanced Package & Systems Symposium Pub Date : 2010-11-22 DOI: 10.1109/EPEPS.2010.5642795
Mahendrasing Patil, A. Brahme, Michael Shust, K. Coates, Shubhada Thatte, Sreekanth Soman, K. Kumar
{"title":"Chip-package-board co-design for complex System-on-Chip (SoC)","authors":"Mahendrasing Patil, A. Brahme, Michael Shust, K. Coates, Shubhada Thatte, Sreekanth Soman, K. Kumar","doi":"10.1109/EPEPS.2010.5642795","DOIUrl":"https://doi.org/10.1109/EPEPS.2010.5642795","url":null,"abstract":"Device scaling has allowed us to pack more functionality in a smaller die area. The ever increasing number of interfaces and the complexity of advanced SoCs force custom package design for almost every device rather than using a standard of the shelf package. The time-to-market window is shrinking with rapidly growing demand in the consumer market. To meet package performance with reduced package size and cost constraints, early evaluation of package and board routing is required. Floorplan of today's complex SoCs' is driven not only by the package but also board and overall system design. Chip-Package-Board co-design is obligatory to meet performance and schedule requirements as well as to reduce the system cost. This paper talks about the co-design challenges on a 40nm complex SoC implementation.","PeriodicalId":185326,"journal":{"name":"2010 IEEE Electrical Design of Advanced Package & Systems Symposium","volume":"99 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124330176","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
High speed DDR interface timing closure 高速DDR接口定时关闭
2010 IEEE Electrical Design of Advanced Package & Systems Symposium Pub Date : 2010-11-22 DOI: 10.1109/EPEPS.2010.5642791
Sreekanth Soman, A. Brahme, Mahendrasing Patil
{"title":"High speed DDR interface timing closure","authors":"Sreekanth Soman, A. Brahme, Mahendrasing Patil","doi":"10.1109/EPEPS.2010.5642791","DOIUrl":"https://doi.org/10.1109/EPEPS.2010.5642791","url":null,"abstract":"This paper discusses the challenges in system level timing closure of a high speed DDR interface. The different aspects of the DDR controller, I/O buffer, package and board to be modeled for ensuring stable operation at the targeted speed are described.","PeriodicalId":185326,"journal":{"name":"2010 IEEE Electrical Design of Advanced Package & Systems Symposium","volume":"143 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133361731","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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