高速DDR接口定时关闭

2010 IEEE Electrical Design of Advanced Package & Systems Symposium Pub Date : 2010-11-22 DOI:10.1109/EPEPS.2010.5642791

Sreekanth Soman, A. Brahme, Mahendrasing Patil

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引用次数: 3

摘要

本文讨论了高速DDR接口在系统级时序关闭方面面临的挑战。描述了DDR控制器、I/O缓冲器、封装和电路板的不同方面，以确保在目标速度下稳定运行。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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High speed DDR interface timing closure

This paper discusses the challenges in system level timing closure of a high speed DDR interface. The different aspects of the DDR controller, I/O buffer, package and board to be modeled for ensuring stable operation at the targeted speed are described.

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2010 IEEE Electrical Design of Advanced Package & Systems Symposium

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