2010 IEEE Electrical Design of Advanced Package & Systems Symposium最新文献_第5页

Electrothermal characterization of carbon nanotube field effect transistors (CNTFETs) 碳纳米管场效应晶体管的电热特性研究

2010 IEEE Electrical Design of Advanced Package & Systems Symposium Pub Date : 2010-12-01 DOI: 10.1109/EDAPS.2010.5683041

Chuan-Jia Xing, Lei Liu, W. Yin

引用次数: 0

Hybrid modeling and analysis of power supply noise effects on analog-to-digital converter considering hierarchical PDNs 考虑分层pdn的模数转换器电源噪声影响的混合建模与分析

2010 IEEE Electrical Design of Advanced Package & Systems Symposium Pub Date : 2010-12-01 DOI: 10.1109/EDAPS.2010.5682997

Bumhee Bae, Yujeong Shim, Woojin Lee, Kyoungchoul Koo, Woojin Ahn, Joungho Kim

{"title":"Hybrid modeling and analysis of power supply noise effects on analog-to-digital converter considering hierarchical PDNs","authors":"Bumhee Bae, Yujeong Shim, Woojin Lee, Kyoungchoul Koo, Woojin Ahn, Joungho Kim","doi":"10.1109/EDAPS.2010.5682997","DOIUrl":"https://doi.org/10.1109/EDAPS.2010.5682997","url":null,"abstract":"An analog-to-digital converter (ADC) is an essential device in mixed mode systems. The performance of the ADC, however, is deteriorated by coupled power supply noises through hierarchical chip-PCB power distributed networks (PDNs). In order to design a high-performance system, modeling and analysis of power supply noise effects on the ADC are necessary, as the power supply noise is coupled to the circuit through the hierarchical PDN structure in multilayer PCB substrates. In this paper, a hybrid model is proposed for analysis of power supply noise effects on the ADC. The model combines two modeling mechanisms. First, the coupling ratio of the power supply noise is derived by the combined model of hierarchical PDNs at the PCB and the chip. Second, an analytical model is proposed using equivalent circuits for analysis of the power supply noise effects on the ADC. The ADC is designed using a 0.13um CMOS process. The proposed model and analysis are verified based on a simulation from 100kHz to 4GHz. The performance of the ADC is dominantly affected by characteristics of the on-chip circuit under 100MHz. It is also confirmed that the Effective Number of Bits (ENOB) of the ADC is strongly dependent on the hierarchical PDN impedance over 100MHz. Furthermore, there are peak points caused by inter-modulation (IMD) and cavity resonances of PDN structures.","PeriodicalId":185326,"journal":{"name":"2010 IEEE Electrical Design of Advanced Package & Systems Symposium","volume":"31 10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125701873","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Comparing flip-chip and wire-bond package effects on a receiver low-noise amplifier 比较倒装与线键封装对接收机低噪声放大器的影响

2010 IEEE Electrical Design of Advanced Package & Systems Symposium Pub Date : 2010-12-01 DOI: 10.1109/EDAPS.2010.5683007

K. Lu, T. Horng, F. Han, Hung-Hsiang Cheng, C. Chiu, C. Hung

引用次数: 4

Non-uniform currents on vias and their effects in a parallel-plate environment 平行板环境下通孔上的非均匀电流及其影响

2010 IEEE Electrical Design of Advanced Package & Systems Symposium Pub Date : 2010-12-01 DOI: 10.1109/EDAPS.2010.5683028

S. Muller, X. Duan, R. Rímolo-Donadío, H. Bruns, C. Schuster

引用次数: 13

Jump the Q: A fast jitter tolerance measurement method using Q-statistical model 跳Q:一种利用Q统计模型快速测量抖动容差的方法

2010 IEEE Electrical Design of Advanced Package & Systems Symposium Pub Date : 2010-12-01 DOI: 10.1109/EDAPS.2010.5683044

E. Cheng, J. Kho, Y. L. Tan, Wei Wei Lo, M. Wong

{"title":"Jump the Q: A fast jitter tolerance measurement method using Q-statistical model","authors":"E. Cheng, J. Kho, Y. L. Tan, Wei Wei Lo, M. Wong","doi":"10.1109/EDAPS.2010.5683044","DOIUrl":"https://doi.org/10.1109/EDAPS.2010.5683044","url":null,"abstract":"With high-speed receivers and clock data recovery (CDR) blocks operating at speeds in excess of 10 Gbps, stringent CDR jitter tolerance test criteria are necessary to qualify device reliability. A robust CDR jitter tolerance test should accommodate test criteria with extremely low bit error rate (BER) values, usually 10−12 or lower for typical industrial protocols. Using conventional methods, the time required to measure a complete set of CDR jitter tolerance values can stretch into weeks depending on the data rate. In general, measurement time increases tenfold for a similar tenfold reduction in BER. This translates to prohibitively long measurement times for BER values of 10−15 and lower. Statistical extrapolation for low BER measurement such as Q scale has been widely used in the industry, but this is only applied for transmitter measurements, specifically jitter measurements. This paper introduces a novel, fast measurement method for receiver testing based on the Q-statistical method to predict the BER for high-volume data transmission based on small sample data sets. Experimental data using this method show that extrapolated jitter tolerance values for BER values down to 10−15 can achieve an accuracy of 1.25 mUI. This innovative method improves the efficiency of jitter tolerance tests by significantly reducing measurement time. Furthermore, the method allows for the extension of measurement scope to cover previously unattainable jitter tolerance values for lower BER values. With these advantages, full jitter tolerance characterization on Altera Stratix® IV GX devices successfully meets very aggressive product rollout and time-to-market schedule, even with measurements for 24 protocols and support for BER of 10−12 and lower.","PeriodicalId":185326,"journal":{"name":"2010 IEEE Electrical Design of Advanced Package & Systems Symposium","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125363386","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Design of a true single-phase-clock divider in 0.13µm CMOS 0.13µm CMOS中真正的单相时钟分压器的设计

2010 IEEE Electrical Design of Advanced Package & Systems Symposium Pub Date : 2010-12-01 DOI: 10.1109/EDAPS.2010.5683039

Lei Wang, Y. Xiong, San-Ming Hu, T. Lim

引用次数: 0

Augmented EPA with augmented EFIE method for packaging analysis 增强EPA与增强EFIE方法包装分析

2010 IEEE Electrical Design of Advanced Package & Systems Symposium Pub Date : 2010-12-01 DOI: 10.1109/EDAPS.2010.5683002

Zu-Hui Ma, Lijun Jiang, W. Chew, M. Li, Z. Qian

引用次数: 4

Conformal shielding investigation for SiP modules SiP模块的共形屏蔽研究

2010 IEEE Electrical Design of Advanced Package & Systems Symposium Pub Date : 2010-12-01 DOI: 10.1109/EDAPS.2010.5683022

Chun-Hsiang Huang, Chih-Ying Hsiao, Chuen-De Wang, Tonny Chen, Liao Kuo-Hsien, Tzong-Lin Wu

引用次数: 12

Performance analyse on millimetre-wave bonding-wire interconnection 毫米波键合线互连性能分析

2010 IEEE Electrical Design of Advanced Package & Systems Symposium Pub Date : 2010-12-01 DOI: 10.1109/EDAPS.2010.5683034

Jiankang Li, Y. Xiong, Sanming Hu, W. Goh, Debin Hou, Wen Wu

引用次数: 14

Bandwidth and density reduction of tabulated data using causality checking 使用因果关系检查减少表列数据的带宽和密度

2010 IEEE Electrical Design of Advanced Package & Systems Symposium Pub Date : 2010-12-01 DOI: 10.1109/EDAPS.2010.5683023

B. Young

引用次数: 6