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2010 IEEE Electrical Design of Advanced Package & Systems Symposium最新文献

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Stub length prediction for back-drilled vias using a fast via tool 使用快速过孔工具预测后钻过孔的短段长度
2010 IEEE Electrical Design of Advanced Package & Systems Symposium Pub Date : 2010-12-01 DOI: 10.1109/EDAPS.2010.5683010
Jianmin Zhang, Q. Chen, Hanfeng Wang, J. Fan, A. Orlandi, J. Drewniak
{"title":"Stub length prediction for back-drilled vias using a fast via tool","authors":"Jianmin Zhang, Q. Chen, Hanfeng Wang, J. Fan, A. Orlandi, J. Drewniak","doi":"10.1109/EDAPS.2010.5683010","DOIUrl":"https://doi.org/10.1109/EDAPS.2010.5683010","url":null,"abstract":"This paper presents a fast via tool to predict the via stub length after back-drilling. The fast via tool is developed associated with the physics based via model and is combined with the calculation of plane impedance and via capacitance block by block. The entire via model is built by connecting those via blocks one after another accordingly. The plane impedance is calculated from an analytical formula and the via capacitance is computed from the point of view of energy by solving the potential distribution on each via block using FEM. Via stub length is predicted with the observation of strong resonant trough on the insertion loss, which can be in single-ended mode or mixed mode. Two cases, one signal via surrounded by eight ground vias and four signal vias surrounded by four ground vias, are used to verify the modelling accuracy of the fast via tool by correlating to the measurements. The third case is about via stub length extraction as well as the sensitivity investigation between the stub length and the resonant frequency.","PeriodicalId":185326,"journal":{"name":"2010 IEEE Electrical Design of Advanced Package & Systems Symposium","volume":"359 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115470352","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Near-field to far-field prediction for high-speed board using an empirical approach 基于经验方法的高速电路板近场到远场预测
2010 IEEE Electrical Design of Advanced Package & Systems Symposium Pub Date : 2010-12-01 DOI: 10.1109/EDAPS.2010.5683026
M. Oswal, K. See, Weishan Soh, Weng-Yew Chang, Lin Biao Wang, W. Koh, Hazel Low
{"title":"Near-field to far-field prediction for high-speed board using an empirical approach","authors":"M. Oswal, K. See, Weishan Soh, Weng-Yew Chang, Lin Biao Wang, W. Koh, Hazel Low","doi":"10.1109/EDAPS.2010.5683026","DOIUrl":"https://doi.org/10.1109/EDAPS.2010.5683026","url":null,"abstract":"This paper describes a methodology to predict far-field (FF) emissions from a high-speed board based on the fields measured in the near-field (NF) region. The NF to FF transformation is based upon an empirical relationship between the measured fields in both the NF and FF regions. Initial results show that the predicted FF emissions from a high-speed board provide the designer a good confidence on the compliance of regulatory emission limits.","PeriodicalId":185326,"journal":{"name":"2010 IEEE Electrical Design of Advanced Package & Systems Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131306625","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
RF substrates yield improvement using package-chip co-design and on-chip calibration 射频基板使用封装芯片协同设计和片上校准来提高产量
2010 IEEE Electrical Design of Advanced Package & Systems Symposium Pub Date : 2010-12-01 DOI: 10.1109/EDAPS.2010.5683018
A. Goyal, M. Swaminathan, A. Chatterjee
{"title":"RF substrates yield improvement using package-chip co-design and on-chip calibration","authors":"A. Goyal, M. Swaminathan, A. Chatterjee","doi":"10.1109/EDAPS.2010.5683018","DOIUrl":"https://doi.org/10.1109/EDAPS.2010.5683018","url":null,"abstract":"In this paper, yield improvement methodology is proposed for RF substrates with embedded RF passive circuitry. The proposed methodology introduces a concept of package-chip co-design and on-chip calibration of active circuitry for the yield improvement of off-chip passive embedded RF filters. RF receiver architecture for the package-chip co-design and on-chip calibration technique is presented. Using the proposed methodology, it is shown that the yield of RF substrates is improved from 88% to 98%. Also, the measurements results are presented.","PeriodicalId":185326,"journal":{"name":"2010 IEEE Electrical Design of Advanced Package & Systems Symposium","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125409159","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
High-speed electromagnetic field simulation by HIE-FDTD method with GPGPU 基于GPGPU的高速电磁场时域有限差分仿真
2010 IEEE Electrical Design of Advanced Package & Systems Symposium Pub Date : 2010-12-01 DOI: 10.1109/EDAPS.2010.5683040
M. Unno, H. Asai
{"title":"High-speed electromagnetic field simulation by HIE-FDTD method with GPGPU","authors":"M. Unno, H. Asai","doi":"10.1109/EDAPS.2010.5683040","DOIUrl":"https://doi.org/10.1109/EDAPS.2010.5683040","url":null,"abstract":"The HIE(Hybrid Implicit-Explicit)-FDTD method is very useful for the simulation of computational domain with thin cells. This paper describes the HIE-FDTD method with GPGPU(General Purpose computing on Graphic Processing Unit) for massively parallel electromagnetic field simulation. First, the properties of the HIE-FDTD method are explained. Next, 3D HIE-FDTD method with CUDA is implemented. Finally, it is shown that the performance of the HIE-FDTD method by GPGPU is much superior to the HIE-FDTD method with single CPU.","PeriodicalId":185326,"journal":{"name":"2010 IEEE Electrical Design of Advanced Package & Systems Symposium","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127358501","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Study of power/ground plane separation on radiated emission suppression 电源/地平面分离对辐射发射抑制的研究
2010 IEEE Electrical Design of Advanced Package & Systems Symposium Pub Date : 2010-12-01 DOI: 10.1109/EDAPS.2010.5683024
Weishan Soh, Weng-Yew Chang, K. See, M. Oswal, W. Koh, Hazel Low
{"title":"Study of power/ground plane separation on radiated emission suppression","authors":"Weishan Soh, Weng-Yew Chang, K. See, M. Oswal, W. Koh, Hazel Low","doi":"10.1109/EDAPS.2010.5683024","DOIUrl":"https://doi.org/10.1109/EDAPS.2010.5683024","url":null,"abstract":"In today's high-speed board design, decoupling using on-board capacitors are necessary to provide stable DC power and to suppress radiated emission from the board. At the higher frequency beyond 300 MHz, one has to rely on the capacitance offered by the power-ground plane pair in multi-layer stackup to provide effective decoupling. This paper provides an in-depth analysis on the suppression of board emission with the reduction of plane separation.","PeriodicalId":185326,"journal":{"name":"2010 IEEE Electrical Design of Advanced Package & Systems Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130628877","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Power distribution TSVs induced core switching noise 电源分配tsv诱导的铁芯开关噪声
2010 IEEE Electrical Design of Advanced Package & Systems Symposium Pub Date : 2010-12-01 DOI: 10.1109/EDAPS.2010.5683008
W. Ahmad, R. Kanth, Qiang Chen, Li-Rong Zheng, H. Tenhunen
{"title":"Power distribution TSVs induced core switching noise","authors":"W. Ahmad, R. Kanth, Qiang Chen, Li-Rong Zheng, H. Tenhunen","doi":"10.1109/EDAPS.2010.5683008","DOIUrl":"https://doi.org/10.1109/EDAPS.2010.5683008","url":null,"abstract":"Size of on-chip interconnects as well as the supply voltage is reducing with each technology node whereas the operating speed is increasing in modern VLSI design. Today, the package inductance and resistance has been reduced to such an extent that core switching noise caused by on-chip inductance and on-chip resistance is gaining importance as compared to I/O drivers switching noise. Both on-chip inductance and skin effect are prime players at frequencies of the order of GHz. The problem is further aggravated when chips are interconnected through TSVs to form a 3D integrated stack in order to achieve low form factor and high integration density. In this paper we analysed peak core switching noise in a 3D stack of integrated chips interconnected through power distribution TSV pairs, through our comprehensive mathematical model which has been proved to be quite accurate as compared to SPICE. We analysed the effect of number of chips in a 3D stack, rise time, decoupling capacitance, and skin effect on power distribution TSVs induced core switching noise in this paper.","PeriodicalId":185326,"journal":{"name":"2010 IEEE Electrical Design of Advanced Package & Systems Symposium","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115041013","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Effect of ground plane design for WLP with signal integrity modeling and analysis 基于信号完整性建模与分析的地平面设计对WLP的影响
2010 IEEE Electrical Design of Advanced Package & Systems Symposium Pub Date : 2010-12-01 DOI: 10.1109/EDAPS.2010.5682993
Glen Siew, Tee Tong Yan, Chen Haoyang, Serine Soh, Kim Jong Heon
{"title":"Effect of ground plane design for WLP with signal integrity modeling and analysis","authors":"Glen Siew, Tee Tong Yan, Chen Haoyang, Serine Soh, Kim Jong Heon","doi":"10.1109/EDAPS.2010.5682993","DOIUrl":"https://doi.org/10.1109/EDAPS.2010.5682993","url":null,"abstract":"Analysis of ground plane design effect for Wafer Level Package (WLP) through advance electrical modeling and simulation for chip-package-board signal integrity co-design was carried out. Increase in information transfer rates is greatly limited by bandwidth of communication channel at PCB board receiver due to channel loss, signal cross-talk, and signal distortion which are critical factors affecting signal integrity of channel and high-speed links such as LVDS, SSTL, LVTTL, LVCMOS and PCI-X. In this work, ground plane design approaches of 2 metal-layer WLP were studied to enhance the signal margin of high-speed signals.","PeriodicalId":185326,"journal":{"name":"2010 IEEE Electrical Design of Advanced Package & Systems Symposium","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130084534","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Design of a miniaturized balun using Low Temperature Co-fired Ceramic Technology 利用低温共烧陶瓷技术设计小型平衡器
2010 IEEE Electrical Design of Advanced Package & Systems Symposium Pub Date : 2010-12-01 DOI: 10.1109/EDAPS.2010.5682998
Jiang Wan-bing, J. Long, Hu Ji-gang, Yang Shi-zhao
{"title":"Design of a miniaturized balun using Low Temperature Co-fired Ceramic Technology","authors":"Jiang Wan-bing, J. Long, Hu Ji-gang, Yang Shi-zhao","doi":"10.1109/EDAPS.2010.5682998","DOIUrl":"https://doi.org/10.1109/EDAPS.2010.5682998","url":null,"abstract":"This paper presents a novel miniaturized balun using Low Temperature Co-fired Ceramic (LTCC) Technology. Lumped capacitors are employed in the balun, so that the electrical length of the coupled line can be reduced greatly compared to conventional Marchand balun. The even-odd mode method is used to analyze it, and a novel three dimensional (3D) structure is presented. A spiral broadside coupled strip-line is adopted to realize the proposed miniaturized multi-layer balun. The proposed balun achieves ±0.1dB amplitude balance and ±0.5° phase balance, with over 20dB return loss from 2.4GHz to 2.5GHz, which can be widely used as a standard component in wireless communication.","PeriodicalId":185326,"journal":{"name":"2010 IEEE Electrical Design of Advanced Package & Systems Symposium","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126636379","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Design of TEM cell and high sensitive probe for EMI analysis of built-in Webcam module 内置摄像头模块电磁干扰分析用TEM单元和高灵敏度探头的设计
2010 IEEE Electrical Design of Advanced Package & Systems Symposium Pub Date : 2010-12-01 DOI: 10.1109/EDAPS.2010.5683030
Han-Nien Lin, Chung-Wei Kuo, Jhih-Min Liao, Jian-li Dong
{"title":"Design of TEM cell and high sensitive probe for EMI analysis of built-in Webcam module","authors":"Han-Nien Lin, Chung-Wei Kuo, Jhih-Min Liao, Jian-li Dong","doi":"10.1109/EDAPS.2010.5683030","DOIUrl":"https://doi.org/10.1109/EDAPS.2010.5683030","url":null,"abstract":"Since many extremely susceptible components with low-voltage operation or high sensitivity may be affected from EMI noise and thus degrade their performance, the EMI phenomena from IC becomes an issue for semiconductor industry. In this paper, we have designed a TEM Cell and magnetic field probe with high sensitivity and spatial resolution, in accordance with the IC-EMI measurement standard IEC 61967–2 [1] and IEC 61967–3 [2] respectively. The goal is to setup a more accurate measurement of the noise source location and the corresponding frequency bands to analyze the platform noise effect. The operating frequency of TEM Cell has been raised up to 2.43 GHz. Two identical IC for Webcam module with some minor modifications were used for EMI measurement and further analysis for the interference effects.","PeriodicalId":185326,"journal":{"name":"2010 IEEE Electrical Design of Advanced Package & Systems Symposium","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122218325","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Power supply noise evaluation with on-chip noise monitoring for various decoupling schemes of SiP 基于片上噪声监测的各种SiP解耦方案的电源噪声评估
2010 IEEE Electrical Design of Advanced Package & Systems Symposium Pub Date : 2010-12-01 DOI: 10.1109/EDAPS.2010.5682992
T. Okumura, Y. Oizono, Y. Nabeshima, T. Sudo
{"title":"Power supply noise evaluation with on-chip noise monitoring for various decoupling schemes of SiP","authors":"T. Okumura, Y. Oizono, Y. Nabeshima, T. Sudo","doi":"10.1109/EDAPS.2010.5682992","DOIUrl":"https://doi.org/10.1109/EDAPS.2010.5682992","url":null,"abstract":"Power integrity design is a critical issue in system-in-packages (SiP's). In particular, power supply disturbance excited by simultaneous switching output (SSO) noise, or core circuits is serious in a 3D stacked die packages. Therefore, decoupling schemes in such SiP's must be carefully designed to reduce the impedance of power distribution network (PDN) as low as possible up to high frequency range and to avoid the parallel resonance occurred by chip-package connection. In this paper, a test chip was designed and fabricated to generate noise and to monitor on-chip power supply noise. Then, a power noise evaluation system has been established. Power supply noise on core circuits was measured with a noise monitoring circuit. The noise on output buffer circuit was measured by a fixed high/low method. Power supply noises were examined in various decoupling schemes. They are with embedded SMD capacitors inside interposer, and SMD capacitors mounted on the backside of interposer along with on-chip capacitance.","PeriodicalId":185326,"journal":{"name":"2010 IEEE Electrical Design of Advanced Package & Systems Symposium","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117286746","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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