Effect of ground plane design for WLP with signal integrity modeling and analysis

Abstract

Analysis of ground plane design effect for Wafer Level Package (WLP) through advance electrical modeling and simulation for chip-package-board signal integrity co-design was carried out. Increase in information transfer rates is greatly limited by bandwidth of communication channel at PCB board receiver due to channel loss, signal cross-talk, and signal distortion which are critical factors affecting signal integrity of channel and high-speed links such as LVDS, SSTL, LVTTL, LVCMOS and PCI-X. In this work, ground plane design approaches of 2 metal-layer WLP were studied to enhance the signal margin of high-speed signals.