{"title":"高速伺服器的封装设计","authors":"B. Young, A. Bhandal","doi":"10.1109/EDAPS.2010.5682990","DOIUrl":null,"url":null,"abstract":"High-speed SerDes signals are significantly distorted by the time they leave the package. The distortion is caused by excess capacitive loading at points along the signal path, causing reflections. The reflections can be minimized through design modifications, added structures for compensation, filters, and characteristic impedance shifts.","PeriodicalId":185326,"journal":{"name":"2010 IEEE Electrical Design of Advanced Package & Systems Symposium","volume":"37 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Package design for high-speed SerDes\",\"authors\":\"B. Young, A. Bhandal\",\"doi\":\"10.1109/EDAPS.2010.5682990\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"High-speed SerDes signals are significantly distorted by the time they leave the package. The distortion is caused by excess capacitive loading at points along the signal path, causing reflections. The reflections can be minimized through design modifications, added structures for compensation, filters, and characteristic impedance shifts.\",\"PeriodicalId\":185326,\"journal\":{\"name\":\"2010 IEEE Electrical Design of Advanced Package & Systems Symposium\",\"volume\":\"37 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2010-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2010 IEEE Electrical Design of Advanced Package & Systems Symposium\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EDAPS.2010.5682990\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 IEEE Electrical Design of Advanced Package & Systems Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EDAPS.2010.5682990","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
High-speed SerDes signals are significantly distorted by the time they leave the package. The distortion is caused by excess capacitive loading at points along the signal path, causing reflections. The reflections can be minimized through design modifications, added structures for compensation, filters, and characteristic impedance shifts.
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