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2010 IEEE Electrical Design of Advanced Package & Systems Symposium最新文献

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Power noise suppression techniques using spiral resonator in high-speed PCB 高速PCB中螺旋谐振器的功率噪声抑制技术
2010 IEEE Electrical Design of Advanced Package & Systems Symposium Pub Date : 2010-12-01 DOI: 10.1109/EDAPS.2010.5683006
Tong-Ho Chung, Hee-Do Kang, J. Yook
{"title":"Power noise suppression techniques using spiral resonator in high-speed PCB","authors":"Tong-Ho Chung, Hee-Do Kang, J. Yook","doi":"10.1109/EDAPS.2010.5683006","DOIUrl":"https://doi.org/10.1109/EDAPS.2010.5683006","url":null,"abstract":"In this paper, to the aim of more than 10 dB power noise suppression, investigation of spiral resonators applied in the vicinity of the practical high-speed digital circuit. Their performances are characterized in terms of their capability to effectively suppress simultaneous switching noise in the frequency region of interest with small occupying area on the power distribution network. As a starting point, the maximum order of harmonic up to which the most energy of clock signal is concentrated is estimated by power spectrum analysis for practical high-speed digital circuit. Then, design parameters of a spiral resonator such as the width, the gap and the number of turns were simulated to determine the suppression level and bandwitdh in DDR3 signal. Numerical results are given in order to illustrate the effectiveness of noise suppression of spiral resonator and to validate the theoretical analysis.","PeriodicalId":185326,"journal":{"name":"2010 IEEE Electrical Design of Advanced Package & Systems Symposium","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114777812","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
FdSPICE: A parallel simulation technique for lossy and dispersive interconnect networks FdSPICE:一种用于损耗和色散互连网络的并行仿真技术
2010 IEEE Electrical Design of Advanced Package & Systems Symposium Pub Date : 2010-12-01 DOI: 10.1109/EDAPS.2010.5683035
Jian Wang, M. Tang, Lizhuang Ma, Junfa Mao
{"title":"FdSPICE: A parallel simulation technique for lossy and dispersive interconnect networks","authors":"Jian Wang, M. Tang, Lizhuang Ma, Junfa Mao","doi":"10.1109/EDAPS.2010.5683035","DOIUrl":"https://doi.org/10.1109/EDAPS.2010.5683035","url":null,"abstract":"This paper presents a parallel algorithm for the simulation of large complex interconnect networks with frequency-dependent parameters. The equivalent transmission line model, which is suitable for time-domain simulation, is introduced for the modeling of dispersive interconnects. By means of the equivalent multi-port model, the interconnects are separated from other circuit elements, and thus makes the parallel simulation feasible. Based on the proposed technique, a program named FdSPICE is developed for parallel simulation of large interconnect networks. The accuracy and efficiency of FdSPICE are demonstrated by numerical examples.","PeriodicalId":185326,"journal":{"name":"2010 IEEE Electrical Design of Advanced Package & Systems Symposium","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127140240","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
NBPE: Neural network based power estimation simulator for specification design 用于规范设计的基于神经网络的功率估计模拟器
2010 IEEE Electrical Design of Advanced Package & Systems Symposium Pub Date : 2010-12-01 DOI: 10.1109/EDAPS.2010.5683004
L. Hou, Xiaohong Peng, Shuqin Geng, Jinhui Wang, Wu-chen Wu
{"title":"NBPE: Neural network based power estimation simulator for specification design","authors":"L. Hou, Xiaohong Peng, Shuqin Geng, Jinhui Wang, Wu-chen Wu","doi":"10.1109/EDAPS.2010.5683004","DOIUrl":"https://doi.org/10.1109/EDAPS.2010.5683004","url":null,"abstract":"This paper forwards a neural network based VLSI power estimation Simulator (NBPE) for VLSI specification design with a graphical user interface developed. The user can enter parameters from VLSI specification such as IO number, frequency, flash depth and parameters on neural network structure such as layer number, learning algorithm etc. This simulator then estimate VLSI's power based on given information. Power estimation results can be used to adjust VLSI specification design before further implementation. Available as an executable code, the simulator can run on various platforms.","PeriodicalId":185326,"journal":{"name":"2010 IEEE Electrical Design of Advanced Package & Systems Symposium","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128980273","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Evaluation of IBIS modelling techniques for signal integrity simulations without and with package parasitics 无封装寄生和有封装寄生信号完整性仿真的IBIS建模技术评价
2010 IEEE Electrical Design of Advanced Package & Systems Symposium Pub Date : 2010-12-01 DOI: 10.1109/EDAPS.2010.5683003
Y. Ji, K. Mouthaan, N. Venkatarayalu
{"title":"Evaluation of IBIS modelling techniques for signal integrity simulations without and with package parasitics","authors":"Y. Ji, K. Mouthaan, N. Venkatarayalu","doi":"10.1109/EDAPS.2010.5683003","DOIUrl":"https://doi.org/10.1109/EDAPS.2010.5683003","url":null,"abstract":"Input/Output Buffer Information Specification (IBIS) models are widely used in signal integrity analysis because of their ability to protect proprietary information and to reduce simulation time when compared to full SPICE simulations. Generation of IBIS models with I/V and V/T data from a full SPICE model of a typical digital buffer without and with package parasitics is investigated in this paper. Several different IBIS model generation strategies to incorporate package effects are validated with the full SPICE model in order to provide a suitable approach. In addition, the accuracy of IBIS simulations in HSPICE and ADS is investigated.","PeriodicalId":185326,"journal":{"name":"2010 IEEE Electrical Design of Advanced Package & Systems Symposium","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130471964","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Chip power current source modeling method applicable to arbitrary data patterns 芯片电源电流源建模方法适用于任意数据模式
2010 IEEE Electrical Design of Advanced Package & Systems Symposium Pub Date : 2010-12-01 DOI: 10.1109/EDAPS.2010.5683015
Sang-Hyeon Han, Se-dong Song, Hark-Byeong Park
{"title":"Chip power current source modeling method applicable to arbitrary data patterns","authors":"Sang-Hyeon Han, Se-dong Song, Hark-Byeong Park","doi":"10.1109/EDAPS.2010.5683015","DOIUrl":"https://doi.org/10.1109/EDAPS.2010.5683015","url":null,"abstract":"A model called ICEM (Integrated Circuits Emission Model) has been widely studied to be used in many various applications. This paper deals with the method of making chip power current source models that can be applied efficiently to an arbitrary input data patterns. It is aimed at modeling radiated and conducted emissions of integrated circuits on printed circuit boards, practically.","PeriodicalId":185326,"journal":{"name":"2010 IEEE Electrical Design of Advanced Package & Systems Symposium","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116663909","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Neural network techniques for fast parametric modeling of vias on multilayered circuit packages 多层电路封装上过孔快速参数化建模的神经网络技术
2010 IEEE Electrical Design of Advanced Package & Systems Symposium Pub Date : 2010-12-01 DOI: 10.1109/EDAPS.2010.5682999
Yazi Cao, Qi-jun Zhang
{"title":"Neural network techniques for fast parametric modeling of vias on multilayered circuit packages","authors":"Yazi Cao, Qi-jun Zhang","doi":"10.1109/EDAPS.2010.5682999","DOIUrl":"https://doi.org/10.1109/EDAPS.2010.5682999","url":null,"abstract":"This paper provides an overview of recent advances of neural network techniques for fast and parametric modeling of vias on the multilayered circuit packages. First, we review a space-mapping neural network technique for broadband and completely parametric modeling of vias. This technique exploits the merits of space-mapping technology and incorporates an equivalent circuit into the model structure. The neural network is trained to learn the multi-dimensional mapping between the geometrical variables and the values of independent circuit elements in the equivalent circuit. Once trained with the EM data, this model provides accurate and fast prediction of the EM behavior of vias with geometry parameters as variables. We also review a combined neural networks and transfer functions technique for via modeling. This technique is capable of providing accurate simulation models even if an equivalent circuit is not available. It retains the EM level accuracy and reduces CPU time significantly compared to EM simulator. Experiments in comparison with measurement data and EM simulations are included to demonstrate the merits of these neural network techniques.","PeriodicalId":185326,"journal":{"name":"2010 IEEE Electrical Design of Advanced Package & Systems Symposium","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123158636","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Electrothermal modelling of through silicon via (TSV) interconnects 硅通孔(TSV)互连的电热建模
2010 IEEE Electrical Design of Advanced Package & Systems Symposium Pub Date : 2010-12-01 DOI: 10.1109/EDAPS.2010.5683011
Xiao-Peng Wang, Wensheng Zhao, W. Yin
{"title":"Electrothermal modelling of through silicon via (TSV) interconnects","authors":"Xiao-Peng Wang, Wensheng Zhao, W. Yin","doi":"10.1109/EDAPS.2010.5683011","DOIUrl":"https://doi.org/10.1109/EDAPS.2010.5683011","url":null,"abstract":"Electrothermal effects in through silicon via (TSV) interconnects are investigated in this paper. The temperature-dependent TSV capacitance is calculated with MOS effect in silicon substrate considered. The per-unit-length resistance and inductance of TSV arrays made of different filling materials are extracted numerically with the partial-element equivalent-circuit (PEEC) method, and insertion losses of some TSV pairs are examined for different silicon substrate resistivities. The electrothermal responses of some TSV arrays made of different materials are also investigated using the modified time-domain finite-element method (TD-FEM).","PeriodicalId":185326,"journal":{"name":"2010 IEEE Electrical Design of Advanced Package & Systems Symposium","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123626802","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Application of ADE-LIM to multiconductor transmission lines with nonlinear drivers and terminations ADE-LIM在非线性驱动器和终端多导体传输线中的应用
2010 IEEE Electrical Design of Advanced Package & Systems Symposium Pub Date : 2010-12-01 DOI: 10.1109/EDAPS.2010.5683037
H. Kurobe, T. Sekine, H. Asai
{"title":"Application of ADE-LIM to multiconductor transmission lines with nonlinear drivers and terminations","authors":"H. Kurobe, T. Sekine, H. Asai","doi":"10.1109/EDAPS.2010.5683037","DOIUrl":"https://doi.org/10.1109/EDAPS.2010.5683037","url":null,"abstract":"This paper describes an application technique of the alternating direction explicit-latency insertion method (ADE-LIM) to multiconductor transmission lines (MTLs) with nonlinear drivers and terminations. The ADE-LIM is an improved method of the LIM for the fast transient analysis of large interconnects. In this paper, MTLs are modeled into a per-unit-length equivalent circuit with tightly coupled elements, and driven and terminated by nonlinear elements such as diodes and CMOS inverters. To deal with these types of elements in the ADE-LIM simulation, ADE-based formulations including coupled and nonlinear elements are proposed. Numerical results show that the ADE-LIM is about 6.5 times faster than the LIM with appropriate accuracy.","PeriodicalId":185326,"journal":{"name":"2010 IEEE Electrical Design of Advanced Package & Systems Symposium","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121594231","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Modeling and analysis of electrothermal effects on global ULSI interconnects 全球ULSI互连的电热效应建模与分析
2010 IEEE Electrical Design of Advanced Package & Systems Symposium Pub Date : 2010-12-01 DOI: 10.1109/EDAPS.2010.5683036
Xiaochun Li, Jialing Tong, Yan Shao, Junfa Mao
{"title":"Modeling and analysis of electrothermal effects on global ULSI interconnects","authors":"Xiaochun Li, Jialing Tong, Yan Shao, Junfa Mao","doi":"10.1109/EDAPS.2010.5683036","DOIUrl":"https://doi.org/10.1109/EDAPS.2010.5683036","url":null,"abstract":"In high-performance integrated circuits, electrothermal effects have important implications for both performance and reliability. This paper presents a detailed modeling and analysis of the electrothermal effects of global interconnects. Interconnect Joule heating increases the line temperature whereas the rise of the temperature decreases the power dissipation due to the increase of the line resistance. Therefore, the interconnect temperature profile will be stable when it reaches steady state. Based on these electrothermal coupling effects, an iterative method is proposed to analyze the temperature profile and signal response of global interconnects. The proposed method is proven to be convergent, with accuracy above 98% with respect to 3D solver COMSOL, which uses finite element analysis. It is also shown that neglecting electrothermal coupling will overestimate interconnect temperature and propagation delay.","PeriodicalId":185326,"journal":{"name":"2010 IEEE Electrical Design of Advanced Package & Systems Symposium","volume":"146 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127251938","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
IPD broadband balun design for GSM applications GSM应用的IPD宽带平衡设计
2010 IEEE Electrical Design of Advanced Package & Systems Symposium Pub Date : 2010-12-01 DOI: 10.1109/EDAPS.2010.5683043
K. Chen, Boxiang Fang, Hsiao-Hua Yeh
{"title":"IPD broadband balun design for GSM applications","authors":"K. Chen, Boxiang Fang, Hsiao-Hua Yeh","doi":"10.1109/EDAPS.2010.5683043","DOIUrl":"https://doi.org/10.1109/EDAPS.2010.5683043","url":null,"abstract":"This paper presents the integrated passive device (IPD) broadband balun design by second-order lattice type topology for GSM applications. Analytical expressions of inductance and capacitance values are derived from ABCD matrix with easy making lump element values evaluated accurately. Finally, the two broadband baluns are designed based on silicon substrate for the theory's demonstration which exhibit the amplitude difference lower than 0.8 dB, insertion loss better than −0.8 dB and phase delay difference located at 180 +/− 4 degrees from the frequency of 0.8GHz ∼ 1GHz and 1.5 ∼ 2.1 GHz covering all GSM low/high band.","PeriodicalId":185326,"journal":{"name":"2010 IEEE Electrical Design of Advanced Package & Systems Symposium","volume":"2016 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127445944","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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