On-chip PDN design effects on 3D stacked on-chip PDN impedance based on TSV interconnection

Abstract

This paper presents the analyses of 3D (3 Dimensional) stacked on-chip PDN (Power Distribution Network) impedances, which are composed with on-chip PDNs and TSV (Through Silicon Via) interconnections, and show the various features depending on on-chip PDN designs and 3D stacked chip configurations. Multi-stacked on-chip PDNs with very large capacitances interacting with even very small inductive TSV interconnections induces high PDN impedance peaks in GHz range, where single chip-PDN shows low PDN impedance. As multi-stacked on-chip PDN has larger capacitance, the high PDN impedance peaks appear at lower frequency range due to the relation of on-chip PDN capacitance and TSV inductance. Therefore, analysis and evaluation of on-chip PDN are very important to design 3D stacked chip. First, PDN impedance of single meshed type on-chip PDN is evaluated by the proposed on-chip PDN model and the measurement. Second, by using the evaluated on-chip PDN impedances and simple inductor model of TSV, the PDN impedances of 3D stacked on-chip PDNs is analyzed in consideration with the various on-chip PDN designs and stacked on-chip PDN numbers.