2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)最新文献

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Inverter-Based Fast Transient Response Capacitor-Less LDO 基于逆变器的快速瞬态响应无电容LDO
Jiaojin Shi, Jie Tang, Xiuyin Zhang, Weijing Wu, Mingjian Zhao, Mo Huang
{"title":"Inverter-Based Fast Transient Response Capacitor-Less LDO","authors":"Jiaojin Shi, Jie Tang, Xiuyin Zhang, Weijing Wu, Mingjian Zhao, Mo Huang","doi":"10.1109/EDSSC.2019.8754385","DOIUrl":"https://doi.org/10.1109/EDSSC.2019.8754385","url":null,"abstract":"This paper proposes a fully integrated low dropout regulator (LDO) with fast transient response capability without the need of external off-chip capacitors. Based on the traditional LDO, two inverters are inserted between the gate of the PMOS and the output stage of the error amplifier. At steady state of LDO, the inverter increases the line and load regulation because it acts as a gain stage. At transient state, the inverter provides a fast transient discharge or charge path to the gate of the PMOS transistor. Fast charging and discharging greatly increase the slew rate of the gate, thereby effectively reducing overshoot and undershoot during transient. The proposed LDO is designed by TSMC 65-nm standard CMOS process. The quiescent current of the LDO is 10 uA, and the line and load regulation are 1 mV/V and 0.6 $mu$V/mA, respectively. For an input voltage of 0.7V and an output voltage of 0.5 V, the voltage spike and the recovery time are reduced to 17 mV and 109 ns, respectively, whereas they are more than 250 mV and 5 us for the conventional structure.","PeriodicalId":183887,"journal":{"name":"2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115820182","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Capacitor-less LDO with Fast transient response using Push-Pull Buffer 一种基于推挽缓冲器的快速瞬态响应无电容LDO
Qiang Li, Kai Wang, Jian-jun Zhao
{"title":"A Capacitor-less LDO with Fast transient response using Push-Pull Buffer","authors":"Qiang Li, Kai Wang, Jian-jun Zhao","doi":"10.1109/EDSSC.2019.8753937","DOIUrl":"https://doi.org/10.1109/EDSSC.2019.8753937","url":null,"abstract":"This paper presents a fast transient capacitor-less low-dropout regulator (LDO). A Push-Pull Buffer (PPB) is proposed to drive the pass transistor. The low output resistance of the PPB allows the pole at the gate of the pass transistor to be pushed beyond the unity-gain frequency of the LDO regulation loop. Transient response is improved, the settling time of LDO are $0.2mu mathrm{S}text{@} mathrm{C}_{mathrm{L}}=0mathrm{p}$F and $1.14mu mathrm{S}text{@}mathrm{C}_{mathrm{L}}=100mathrm{p}$F. The input transistors of error amplifier are realized Cascode structure which is used for connecting compensation capacitor Cc. With this structure, RHP zero generated by compensation capacitor is pushed beyond the unity-gain frequency of the LDO regulation loop. And LHP zero generated by the Cc is used to compensate the non-dominate poles. Compensation capacitance is 1pF. The Dynamic Transient Improvement (DTI) circuit is adopted to reduce the ripples of the output voltage of LDO. The proposed LDO can operate from a supply voltage of 2.2V-4V with a minimum dropout voltage of 0. 2V at a maximum 50mA load and quiescent current of 70$mu$A. Only 4pF capacitor is integrated in the chip, the output of LDO can be connected 0- 100pF off-chip capacitor.","PeriodicalId":183887,"journal":{"name":"2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"215 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133538006","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Research on Low Resolution Cell Image Feature Fusion Algorithm Based on Convolutional Neural Network 基于卷积神经网络的低分辨率细胞图像特征融合算法研究
X. Ma, N. Yu
{"title":"Research on Low Resolution Cell Image Feature Fusion Algorithm Based on Convolutional Neural Network","authors":"X. Ma, N. Yu","doi":"10.1109/EDSSC.2019.8754475","DOIUrl":"https://doi.org/10.1109/EDSSC.2019.8754475","url":null,"abstract":"In this paper, a low-resolution image fusion method based on convolutional neural network is proposed for the problem of low resolution, few detail features and difficulty in feature extraction of cell images collected by lensless cell acquisition system. Firstly, the image of the cell collected by the medical microscope is segmented into a single white blood cell image with a resolution of 90 × 90 by image threshold segmentation algorithm, and then downsample it to 9 × 9 and input it into the feature fusion network for training. After the training is converged, a feature fusion model is obtained, and then the white blood cell image collected by the lensless cell collection system is input into the model to synthesize the fused cell image with a resolution of 36 × 36. Further, using image binarization and other algorithms, the nucleoplasmic ratio of the fused cell image can be obtained. Finally, the simulated vacuolar white blood cell image with a resolution of 9 × 9 is mixed with the normal white blood cell test image in different proportions and then tested. The test results show that the fused cell image shows a similar topographical feature to the larger part of the mixed test images. This is of great significance for the diagnosis of medical diseases.","PeriodicalId":183887,"journal":{"name":"2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126247321","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 47GHz Mixed-Mode FMCW Signal Generator for Fast Triangular Chirp Modulation 用于快速三角啁啾调制的47GHz混合模FMCW信号发生器
Guopei Chen, Ruichang Ma, Mengdi Cao, Luqiang Duan, Zhiyuan Chen, W. Deng, B. Chi
{"title":"A 47GHz Mixed-Mode FMCW Signal Generator for Fast Triangular Chirp Modulation","authors":"Guopei Chen, Ruichang Ma, Mengdi Cao, Luqiang Duan, Zhiyuan Chen, W. Deng, B. Chi","doi":"10.1109/EDSSC.2019.8754050","DOIUrl":"https://doi.org/10.1109/EDSSC.2019.8754050","url":null,"abstract":"A 47GHz frequency-modulated continuous-wave (FMCW) radar is presented. A current DAC with a 10bit 1st $Sigma Delta$ modulator is utilized to improve the equivalent DCO frequency resolution. A type-II PLL with the polarity-alternation is proposed to remove the frequency error at turning-around points (TAPs). The rms frequency error is improved 10x with 7GHz bandwidth and 200$mu s$ period, which has been verified by MATLAB/Simulink.","PeriodicalId":183887,"journal":{"name":"2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130435266","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Output-Capacitor-Less LDO with High PSR 具有高PSR的无输出电容LDO
Yue Zhang, N. Yu, Zhiqiang Jiang, Yuanyuan Wu
{"title":"Output-Capacitor-Less LDO with High PSR","authors":"Yue Zhang, N. Yu, Zhiqiang Jiang, Yuanyuan Wu","doi":"10.1109/EDSSC.2019.8754483","DOIUrl":"https://doi.org/10.1109/EDSSC.2019.8754483","url":null,"abstract":"A low-dropout regulator (LDO) with high power supply ripple rejection (PSR) and capacitor-free is presented in this paper. The LDO proposes a PSR enhancement module based on the analysis of the power supply noise transmission path. It uses the Q-reduction circuit to reduce the required on-chip capacitor and the load on the minimum required output. The proposed LDO is implemented in 110nm CMOS process. The simulation results indicate that the total on-chip capacitance required for the designed circuit is 6. 5p. The LDO has a phase margin of more than 6$0^{o}$ in the range of 50uA to 50mA. The optimum PSR of the LDO at low frequency is -109dB. The LDO achieves line and load regulation of 65$mu$V/V and 0.396$mu$V/mA respectively.","PeriodicalId":183887,"journal":{"name":"2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125154755","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
SiC Power Device Evolution Opening a New Era in Power Electronics SiC功率器件的发展开启了电力电子的新时代
K. Ino, M. Miura, Y. Nakano, M. Aketa, Noriaki Kawamoto
{"title":"SiC Power Device Evolution Opening a New Era in Power Electronics","authors":"K. Ino, M. Miura, Y. Nakano, M. Aketa, Noriaki Kawamoto","doi":"10.1109/EDSSC.2019.8754464","DOIUrl":"https://doi.org/10.1109/EDSSC.2019.8754464","url":null,"abstract":"A new era in power electronics has been just opened by commercial introduction of silicon carbide (SiC) MOSFETs in a variety of power electronic systems such as power supplies, renewable energy, transportation, heating, robotics, and electric utility transmission/distribution. The utilization of SiC power devices in these systems can enable significant energy saving because of much lower power-loss devices compared to conventional silicon (Si) power devices. In this paper the progress of SiC power transistors is presented in comparison with Si MOSFETs and IGBTs.","PeriodicalId":183887,"journal":{"name":"2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117100140","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A New dual directional SCR with high holding voltage for High Voltage ESD protection 一种用于高压ESD保护的新型高保持电压双向可控硅
Shiyu Song, Feibo Du, Fei Hou, Wenqiang Song, Zhiwei Liu, Jizhi Liu
{"title":"A New dual directional SCR with high holding voltage for High Voltage ESD protection","authors":"Shiyu Song, Feibo Du, Fei Hou, Wenqiang Song, Zhiwei Liu, Jizhi Liu","doi":"10.1109/EDSSC.2019.8754152","DOIUrl":"https://doi.org/10.1109/EDSSC.2019.8754152","url":null,"abstract":"In this paper, A novel high holding voltage dual-directional SCR (HHV-DDSCR) is proposed. The ESD I-V characteristics of HHV-DDSCR and DDSCR (dual-directional SCR) are simulated with the Sentaurus TCAD software. Compared with the DDSCR, the new HHV-DDSCR dramatically increases the holding voltage from 2V to 14V with relatively stable trigger voltage, which can provide efficient ESD protection for high voltage (HV) ICs. Besides, the influence of the parasitic BJTs in HHV-DDSCR on the device performance has also been studied.","PeriodicalId":183887,"journal":{"name":"2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127017579","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
1024-Electrode Deep Brain Probe Readout Circuit with 1024 Configurable Channels in 55nm CMOS 1024电极深度脑探头读出电路与1024可配置通道在55nm CMOS
Yuze Niu, Yajun Zhu, Wengao Lu, Zhaofeng Huang, Yacong Zhang, Zhongjian Chen
{"title":"1024-Electrode Deep Brain Probe Readout Circuit with 1024 Configurable Channels in 55nm CMOS","authors":"Yuze Niu, Yajun Zhu, Wengao Lu, Zhaofeng Huang, Yacong Zhang, Zhongjian Chen","doi":"10.1109/EDSSC.2019.8754407","DOIUrl":"https://doi.org/10.1109/EDSSC.2019.8754407","url":null,"abstract":"This paper demonstrates a 1024-electrode, 1024-channel, $20mu mathrm{m}times 30mu mathrm{m}$ pixel size, $512times 2$ deep brain probe readout circuit. A high dynamic range hybrid ADC is designed for the brain probe circuit. This proposed ADC bases on a chopped-type quantized structure. A band pass filter is formed by the integrator and chopper to improve SNR of the circuit. Furthermore, dynamic range of the readout circuit is improved since a non-uniformity circuit is implemented in-pixel. By in-pixel quantization of signals detected by electrodes, each electrode matches specific channel. As a result, even larger array can be output rapidly. Proposed deep brain probe circuit is realized using 55nm 1P6M CMOS process. Power consumption of single channel is 40$mu$W with noise of 4$mu$V.","PeriodicalId":183887,"journal":{"name":"2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127943904","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
High-Precision Bandgap Voltage Generation Method With Chopper Stabilization Technique 基于斩波稳定技术的高精度带隙电压产生方法
Li Chuang-ze, Han Ben-guang, Guo Zhong-jie, Wu Long-sheng
{"title":"High-Precision Bandgap Voltage Generation Method With Chopper Stabilization Technique","authors":"Li Chuang-ze, Han Ben-guang, Guo Zhong-jie, Wu Long-sheng","doi":"10.1109/EDSSC.2019.8754018","DOIUrl":"https://doi.org/10.1109/EDSSC.2019.8754018","url":null,"abstract":"A Three-level chopping technique to reduce offset caused by mismatch of the Wilson Current-mirror and PNP bipolar transistor is descried and presented. Input referred offset voltage of the PNP transistor is reduced on first level. On second level, Wilson Current-mirror offset is further reduced along with the low frequency 1/f noise caused by the self-biased circuit. The last level is used to reduce offset of self-biased circuit two. The proposed BGR was simulated in a temperature range from -45°C and 125°C. Simulate results showed that the standard deviation of the BGR output voltage without chopping is 9 times higher than that of when chopping is enabled. The proposed three-level chopping technique is verified improving performance characteristics of conventional BGR circuit. The maximum supply current is 36uA and the area of layout is 0. 085mm2 with a standard 0. 13um 1P4M CMOS process.","PeriodicalId":183887,"journal":{"name":"2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133282770","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A Low-Quiescent Current Off-Chip Capacitor-less LDO Regulator with UGCC Compensation 带UGCC补偿的低静态电流片外无电容LDO稳压器
Peiju Liu, S. Huang, Q. Duan, Qian Zhu, Zhen Meng
{"title":"A Low-Quiescent Current Off-Chip Capacitor-less LDO Regulator with UGCC Compensation","authors":"Peiju Liu, S. Huang, Q. Duan, Qian Zhu, Zhen Meng","doi":"10.1109/EDSSC.2019.8754106","DOIUrl":"https://doi.org/10.1109/EDSSC.2019.8754106","url":null,"abstract":"A low quiescent current off-chip capacitor-less low-dropout regulator (CL-LDO) for system on a chip applications is proposed in this study. An error amplifier with embedded unity gain compensation cell (UGCC) circuit is designed to improve both circuit stability and load transient performance. The proposed CL-LDO with a total quiescent current of $1.9~mu text{A}$ and a power supply range from 1.2 to 1.8 V achieves a stable 1 V output. The maximum overshoot voltage is less than 53.1 mV when a maximum current load is 100 mA. The proposed CL-LDO is fabricated in a $0.18~mu text{m}$ standard CMOS process. It occupies an active area of 0.094 mm2.","PeriodicalId":183887,"journal":{"name":"2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115991498","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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