High-Precision Bandgap Voltage Generation Method With Chopper Stabilization Technique

A Three-level chopping technique to reduce offset caused by mismatch of the Wilson Current-mirror and PNP bipolar transistor is descried and presented. Input referred offset voltage of the PNP transistor is reduced on first level. On second level, Wilson Current-mirror offset is further reduced along with the low frequency 1/f noise caused by the self-biased circuit. The last level is used to reduce offset of self-biased circuit two. The proposed BGR was simulated in a temperature range from -45°C and 125°C. Simulate results showed that the standard deviation of the BGR output voltage without chopping is 9 times higher than that of when chopping is enabled. The proposed three-level chopping technique is verified improving performance characteristics of conventional BGR circuit. The maximum supply current is 36uA and the area of layout is 0. 085mm2 with a standard 0. 13um 1P4M CMOS process.