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2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)最新文献

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Predicted Congestion Using a Density-based Fast Neural Network Algorithm in Global Routing 全局路由中基于密度的快速神经网络算法预测拥塞
2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC) Pub Date : 2019-06-12 DOI: 10.1109/EDSSC.2019.8754196
Tong Zhang, Xiaosai Liu, Wenying Tang, Jingxuan Chen, Zhiming Xiao, Fuhai Zhang, Weibo Hu, Zhonghua Zhou, Y. Cheng
{"title":"Predicted Congestion Using a Density-based Fast Neural Network Algorithm in Global Routing","authors":"Tong Zhang, Xiaosai Liu, Wenying Tang, Jingxuan Chen, Zhiming Xiao, Fuhai Zhang, Weibo Hu, Zhonghua Zhou, Y. Cheng","doi":"10.1109/EDSSC.2019.8754196","DOIUrl":"https://doi.org/10.1109/EDSSC.2019.8754196","url":null,"abstract":"As the feature size of devices decreases and the number of transistor interconnect exceeds billions, the runtime of global router becomes a problem in very large-scale integrated circuit design. The congestion prediction in the global routing, which can cost huge time, is one of the most important and challenging problems. In this paper, we propose a density and pins peaks-based fast neural network algorithm (NNA) to predict congestion map. In order to save runtime, traditional prediction methods are replaced by a machine learning method with local density and pins as features. Furthermore, to improve the performance of proposed method, the predictive identification method to specify order of the rip-up and reroute for congested regions is also proposed. Compared with state-of-the-art router, NTHU-Route 2.0, on ISPD08 benchmarks, our method greatly improves the speed of predicting routing congestion information by 1094% in test cases, and saves runtime of the global router.","PeriodicalId":183887,"journal":{"name":"2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124305592","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Advanced 22nm FD-SOI Technolgy With Metal Gate Last Process 先进的22nm FD-SOI技术与金属栅最后工艺
2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC) Pub Date : 2019-06-12 DOI: 10.1109/EDSSC.2019.8754434
Cuiqin Xu, Changfeng Wang, Duanquan Liao
{"title":"Advanced 22nm FD-SOI Technolgy With Metal Gate Last Process","authors":"Cuiqin Xu, Changfeng Wang, Duanquan Liao","doi":"10.1109/EDSSC.2019.8754434","DOIUrl":"https://doi.org/10.1109/EDSSC.2019.8754434","url":null,"abstract":"In this work, we demonstrate an advanced 22 nm fully depleted silicon-on-insulator substrate (FD-SOI) process for very large scale integrated circuit (VLSI). The fabrication process features hybrid substrate, epitaxy for raised source/drain, high-k/metal gate and trench silicidation. For the first time, high-k first/metal-gate last process is applied. The metal-gate last process allows wide choice of metal materials to tune the threshold voltage of the transistor. The fabricated n-type and p-type MOSFETs show very low subthreshold swing and limited drain induced barrier lowering (DIBL) effect.","PeriodicalId":183887,"journal":{"name":"2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133004195","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Effects of Gate Electron Concentration on Organic Thin-Film Transistors with Different Pentacene Thicknesses 栅极电子浓度对不同五苯厚度有机薄膜晶体管的影响
2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC) Pub Date : 2019-06-01 DOI: 10.1109/EDSSC.2019.8753965
Hui Su, Wing-Man Tang, P. Lai
{"title":"Effects of Gate Electron Concentration on Organic Thin-Film Transistors with Different Pentacene Thicknesses","authors":"Hui Su, Wing-Man Tang, P. Lai","doi":"10.1109/EDSSC.2019.8753965","DOIUrl":"https://doi.org/10.1109/EDSSC.2019.8753965","url":null,"abstract":"Bottom-gate pentacene organic thin-film transistors (OTFTs) with different gate electron concentrations and pentacene thicknesses are fabricated. The performances of the OTFTs show dependence on both gate electron concentration and pentacene thickness. Electrons in the gate electrode can reduce the effect from surface optical phonons of the high-k gate dielectric (NdTaON), and so higher gate electron concentration gives better device performance. It is also supported by measurements at 140°C, where the remote phonon scattering is enhanced. Moreover, it is found that the extracted carrier mobility decreases with increasing pentacene thickness, which is attributed to the series resistance of the source/drain electrodes.","PeriodicalId":183887,"journal":{"name":"2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124281955","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Research on Total Reflection Effect for Graphene and its use in Electronic-optical Modulator 石墨烯全反射效应及其在电光调制器中的应用研究
2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC) Pub Date : 2019-06-01 DOI: 10.1109/EDSSC.2019.8754329
Wang Zheng, Kuang Qianwei
{"title":"Research on Total Reflection Effect for Graphene and its use in Electronic-optical Modulator","authors":"Wang Zheng, Kuang Qianwei","doi":"10.1109/EDSSC.2019.8754329","DOIUrl":"https://doi.org/10.1109/EDSSC.2019.8754329","url":null,"abstract":"In this paper, a novel electronic-optical modulator based on total reflection effect of graphene is designed. The geometry of this novel electronic-optical modulator consists of two layers of graphene mixed with boron nitride and a layer of silicon waveguide. This new structure is quite different from the traditional modulator structure (traditional silicon based electro-absorption light modulator). Due to the tunability of the refractive index of graphene, when different voltage is applied to the heterojunction composed of graphene and boron nitride, the depth modulation of incident light at 1550nm wavelength can be achieved. Two different situations are chosen for analysis and calculation. The results show that by changing the magnitude of the voltage on the heterojunction, the light can be easily controlled to achieve or do not achieve the total reflection effect, so as to achieve the depth modulation of light. Finally, the new structure we proposed is almost 100% of the depth, which is incomparable to other structures.","PeriodicalId":183887,"journal":{"name":"2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117127055","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Bonding Wires for Power Modules: from Aluminum to Copper 电源模块的键合线:从铝到铜
2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC) Pub Date : 2019-06-01 DOI: 10.1109/EDSSC.2019.8754216
Nan Jiang, Zilan Li, Chengguo Li, Qiao Wang, Shuxin Zhang, Yingyun Lin
{"title":"Bonding Wires for Power Modules: from Aluminum to Copper","authors":"Nan Jiang, Zilan Li, Chengguo Li, Qiao Wang, Shuxin Zhang, Yingyun Lin","doi":"10.1109/EDSSC.2019.8754216","DOIUrl":"https://doi.org/10.1109/EDSSC.2019.8754216","url":null,"abstract":"Interconnections on the top surface of the chip are now limiting the lifetime of power modules. It is necessary to evaluate the die top interconnection technologies in order to help module manufacturers to find a solution to prolong the lifetime of power modules. In this review, the reliability performance of different die top interconnections, such as Al bond wires, Al-clad Cu bond wires and Cu bond wires are compared. The Cu wire bonding shows the best power cycling capability among the interconnection materials. The failure mechanism has been changed from the bond wire lift-off to the substrate fatigue. The substrate becomes the limitation of the lifetime of power modules.","PeriodicalId":183887,"journal":{"name":"2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127157025","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
NIR-Emitting Erbium/Oxygen-Doped Silicon by Self-Assembled Techniques 自组装技术制备nir发射铒/氧掺杂硅
2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC) Pub Date : 2019-06-01 DOI: 10.1109/EDSSC.2019.8753996
H. Wen, Jiajing He, Jin Hong, F. Yue, Yaping Dan
{"title":"NIR-Emitting Erbium/Oxygen-Doped Silicon by Self-Assembled Techniques","authors":"H. Wen, Jiajing He, Jin Hong, F. Yue, Yaping Dan","doi":"10.1109/EDSSC.2019.8753996","DOIUrl":"https://doi.org/10.1109/EDSSC.2019.8753996","url":null,"abstract":"Self-assembled monolayer (SAM) techniques have been developed to dope silicon surfaces with use of erbium radiation sources. After rapid thermal annealing at 1050°C, surface monolayer structure and dopant concentration distribution were characterized by X-ray photoelectron spectroscopy and secondary ion mass spectroscopy measurements, respectively. A distinctive$^{4}I_{13/2}rightarrow^{4}I_{15/2}$ transition of erbium ion (4f) glowing at 1.54 $mu$m has been observed at room temperature for these Er/O-doped Si samples. With these preliminary results, it is promising to develop room-temperature silicon-based light-emitting devices and lasers on the basis of these bottom-up SAM techniques.","PeriodicalId":183887,"journal":{"name":"2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127526854","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Thin-Barrier InAlN/GaN MISHEMTs Using LPCVD Si3N4as Gate Dielectric
2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC) Pub Date : 2019-06-01 DOI: 10.1109/EDSSC.2019.8753956
Xingye Zhou, Yuangang Wang, X. Tan, G. Gu, Y. Lv, Zhihong Feng
{"title":"Thin-Barrier InAlN/GaN MISHEMTs Using LPCVD Si3N4as Gate Dielectric","authors":"Xingye Zhou, Yuangang Wang, X. Tan, G. Gu, Y. Lv, Zhihong Feng","doi":"10.1109/EDSSC.2019.8753956","DOIUrl":"https://doi.org/10.1109/EDSSC.2019.8753956","url":null,"abstract":"In this work, thin-barrier InAlN/GaN metal-insulator-semiconductor high-electron-mobility transistors (MISHEMTs) with high drain current density and low gate leakage are fabricated and analyzed. In order to suppress the gate leakage, wide-bandgap Si3N4 deposited by low pressure chemical vapor deposition (LPCVD) is used as gate dielectric. The device with a gate length of 1.5 $mu$m demonstrates a drain current of 1.4 A/mm, a gate leakage current of 0.1 $mu$ A/mm, and a current on/off ratio of $sim 10^{7}$. In addition, the impact of passivation on the gate leakage of InAlN/GaN MISHEMT is also investigated.","PeriodicalId":183887,"journal":{"name":"2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123244890","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Ultra-Broad and Angle-Sensitive Terahertz Absorber 超宽角敏感太赫兹吸收器
2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC) Pub Date : 2019-06-01 DOI: 10.1109/EDSSC.2019.8754455
Yu Liu, Wen Huang, Jing Wang, R. Liang, Bin Yu, Jun Xu
{"title":"Ultra-Broad and Angle-Sensitive Terahertz Absorber","authors":"Yu Liu, Wen Huang, Jing Wang, R. Liang, Bin Yu, Jun Xu","doi":"10.1109/EDSSC.2019.8754455","DOIUrl":"https://doi.org/10.1109/EDSSC.2019.8754455","url":null,"abstract":"In this work, we demonstrated an ultra-broad terahertz absorber based on graphene metamaterial on SiO2 substrate which is sensitive to incident angle. The absorption performance can be changed by tuning the Fermi level of graphene. Nearly perfect peak absorption was demonstrated at broad terahertz frequency (1.3 ∼2.2 THz, absorption > 0.99) with Fermi energy of 0.6 eV and graphene width of 13 um. Moreover, the absorber is sensitive to incident angle, indicating the potential applications in angle-sensing.","PeriodicalId":183887,"journal":{"name":"2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123263669","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Quantum Confinement Effects and Electrostatics of Planar Nano-scale Symmetric Double-Gate SOI MOSFETs 平面纳米级对称双栅SOI mosfet的量子约束效应和静电特性
2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC) Pub Date : 2019-06-01 DOI: 10.1109/EDSSC.2019.8754030
A. Medury, Harshit Kansal
{"title":"Quantum Confinement Effects and Electrostatics of Planar Nano-scale Symmetric Double-Gate SOI MOSFETs","authors":"A. Medury, Harshit Kansal","doi":"10.1109/EDSSC.2019.8754030","DOIUrl":"https://doi.org/10.1109/EDSSC.2019.8754030","url":null,"abstract":"The effects of quantum confinement on the charge distribution in planar Double-Gate (DG) SOI (Silicon-on-Insulator) MOSFETs were examined, for sub-10 nm SOI film thicknesses $({mathrm {t_{si}}} leq 10 nm)$, by modeling the potential experienced by the charge carriers as that of an an-harmonic oscillator potential, consistent with the inherent structural symmetry of nanoscale symmetric DGSOI MOSFETs. By solving the 1-D Poisson’s equation using this potential, the results obtained were validated through comparisons with TCAD simulations. The present model satisfactorily predicted the electron density and channel charge density for a wide range of SOI channel thicknesses and gate voltages.","PeriodicalId":183887,"journal":{"name":"2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126620681","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Effects of Annealing Temperatures on the Electrochemical Properties of Silicon Carbide Anode Film for Lithium Ion Battery 退火温度对锂离子电池碳化硅阳极膜电化学性能的影响
2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC) Pub Date : 2019-06-01 DOI: 10.1109/EDSSC.2019.8754064
F. Zhang, Y.Z. Cao, X.X. He, F. Li, J. Shi, Q.A. Huang, X.D. Huang
{"title":"Effects of Annealing Temperatures on the Electrochemical Properties of Silicon Carbide Anode Film for Lithium Ion Battery","authors":"F. Zhang, Y.Z. Cao, X.X. He, F. Li, J. Shi, Q.A. Huang, X.D. Huang","doi":"10.1109/EDSSC.2019.8754064","DOIUrl":"https://doi.org/10.1109/EDSSC.2019.8754064","url":null,"abstract":"The effects of annealing temperatures on the electrochemical properties of silicon carbide anode films are investigated for lithium-ion battery applications. The SiC film shows improved electrochemical performance with increasing annealing temperature. The 900 ° C-annealed SiC film exhibits a reversible capacity of 580 mAh g $^{-1}$ over 100 cycles. Moreover, the 900 ° C-annealed film displays better rate performance with less severe degradation $(sim 12.2$%) than the other two films.","PeriodicalId":183887,"journal":{"name":"2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116105446","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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