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2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)最新文献

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PID Control Considerations for Analog-Digital Hybrid Low-Dropout Regulators (Invited Paper) 模数混合低差稳压器的PID控制(特邀论文)
2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC) Pub Date : 2019-06-12 DOI: 10.1109/EDSSC.2019.8754302
Yan Lu, Mo Huang, R. Martins
{"title":"PID Control Considerations for Analog-Digital Hybrid Low-Dropout Regulators (Invited Paper)","authors":"Yan Lu, Mo Huang, R. Martins","doi":"10.1109/EDSSC.2019.8754302","DOIUrl":"https://doi.org/10.1109/EDSSC.2019.8754302","url":null,"abstract":"This paper briefly introduces the developments of the fully-integrated low-dropout regulators (LDOs) at the beginning. Then, we use the classic proportional-integral-derivative (PID) control theory to discuss and categorize the existing LDOs, and present our design considerations for analog-digital hybrid LDOs in an intuitive way.","PeriodicalId":183887,"journal":{"name":"2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133957252","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Wi-Fi Signal Noise Reduction and Multipath Elimination Based on Autoencoder 基于自编码器的Wi-Fi信号降噪与多径消除
2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC) Pub Date : 2019-06-12 DOI: 10.1109/EDSSC.2019.8753922
Lihong Pi, Chun Zhang, Tuo Xie, Hongyuan Yu, Hongji Wang, Mingchao Yin
{"title":"Wi-Fi Signal Noise Reduction and Multipath Elimination Based on Autoencoder","authors":"Lihong Pi, Chun Zhang, Tuo Xie, Hongyuan Yu, Hongji Wang, Mingchao Yin","doi":"10.1109/EDSSC.2019.8753922","DOIUrl":"https://doi.org/10.1109/EDSSC.2019.8753922","url":null,"abstract":"It is known that the signal is noisy and susceptible to multipath interference in indoor positioning, resulting in a significant error in the processing of the signal. The RSS- assisted cross-correlation (RACC) method can reduce noise and eliminate multipath interference to a certain extent, but too environmentally sensitive. Therefore, in this paper, an effective way of using the deep neural network is proposed to address this problem. Accordingly, the performance of the AutoEncoder in signal noise reduction and multipath interference elimination are discussed. To achieve better results, four AutoEncoder models are put forward, fully connection (FC), convolution plus fully connected (C-FC), convolution plus pooling (C-P), inception (ICP), and the performance of these four models are compared when processing signals with different signal to noise ratio (SNR) and multipath interference. The mean square error (MSE) and the time difference of arrival (TDoA) are the standards for evaluating the effect of signal noise reduction and multipath interference removal. Besides simulated data, we also conducted model performance comparisons in terms of ground truth signal. Experimental results show that fully connected layer is essential to automatic signal coding and the model performs better with the appropriate addition of convolution layer when faced with noise and multipath environments. Notably, compared with RACC method, the TDoA of two resultant signals obtained from the model is more accurate, verified by IEEE 802. 11b WLAN.","PeriodicalId":183887,"journal":{"name":"2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133538861","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 5/10 Gb/s Dual-Mode NRZ/PAM4 CDR in 65-nm CMOS 5/ 10gb /s双模NRZ/PAM4 CDR, 65nm CMOS
2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC) Pub Date : 2019-06-12 DOI: 10.1109/EDSSC.2019.8754128
Ruichang Ma, Mengdi Cao, Guopei Chen, Luqiang Duan, Zheng Song, B. Chi
{"title":"A 5/10 Gb/s Dual-Mode NRZ/PAM4 CDR in 65-nm CMOS","authors":"Ruichang Ma, Mengdi Cao, Guopei Chen, Luqiang Duan, Zheng Song, B. Chi","doi":"10.1109/EDSSC.2019.8754128","DOIUrl":"https://doi.org/10.1109/EDSSC.2019.8754128","url":null,"abstract":"A dual-mode clock and data recovery (CDR) circuit based on phase interpolator (PI) in 65nm CMOS is presented. CDR can recover clock from quadrature phase shift keying (QPSK) modulated signal in non-to-zero (NRZ) mode, and 16 quadrature amplitude modulation (QAM) signal in 4 pulse amplitude modulation (PAM4) mode. An adaptive threshold voltage loop for PAM4 signal is proposed. Simulation results show that CDR can track maximum ± 1000 ppm frequency offset between transmitter and receiver in two modes, and the jitter of the locked clock is 45.2ps in NRZ mode and 47.8ps in PAM4 mode, respectively.","PeriodicalId":183887,"journal":{"name":"2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124037016","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Air Gap Layout optimization Method for Inductor-integrated High-power High-frequency Transformer 电感式集成大功率高频变压器气隙布局优化方法
2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC) Pub Date : 2019-06-12 DOI: 10.1109/EDSSC.2019.8754155
Jianbo Zheng, Wei Chen
{"title":"Air Gap Layout optimization Method for Inductor-integrated High-power High-frequency Transformer","authors":"Jianbo Zheng, Wei Chen","doi":"10.1109/EDSSC.2019.8754155","DOIUrl":"https://doi.org/10.1109/EDSSC.2019.8754155","url":null,"abstract":"Inductor-integrated high-power high-frequency transformer can achieve soft switching of power semiconductor devices and reduce switching loss. That is widely used at high-voltage and high-power applications such as renewable energy grid-connected systems. The method of dividing a single air gap into several air gaps can effectively reduce the additional loss caused by the air gap. However, cutting the air gap in amorphous or nanocrystalline strips commonly used at large-capacity high-frequency applications will break the interlayer insulation and increase the eddy current loss at the core incision. Hence, the number of air gaps should be as few as possible. This paper introduces that three quasi-distributed air gaps can be arranged at three regions of the magnetic core according to the certain rule to effectively decrease winding loss. Finite element analyses (FEA) will be utilized to validate that the proposed method is better than that of the six quasi-distributed air gaps.","PeriodicalId":183887,"journal":{"name":"2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"175 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115951697","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Lane Detection for Track-following Based on Histogram Statistics 基于直方图统计的车道跟踪检测
2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC) Pub Date : 2019-06-12 DOI: 10.1109/EDSSC.2019.8754094
Jianye He, Sha Sun, Debing Zhang, Guangqi Wang, Chun Zhang
{"title":"Lane Detection for Track-following Based on Histogram Statistics","authors":"Jianye He, Sha Sun, Debing Zhang, Guangqi Wang, Chun Zhang","doi":"10.1109/EDSSC.2019.8754094","DOIUrl":"https://doi.org/10.1109/EDSSC.2019.8754094","url":null,"abstract":"Visual navigation technologies such as lane detection have been applied in many fields. A multi-line detection algorithm based on histogram statistics is proposed for the track-following application. After the preprocessing of the original image and projecting, the pixel histogram in the bird view space can be got and the starting points of the lane detection are obtained by filtering and clustering the histogram. Subsequently, the sliding windows are moved to capture the pixels on the lines. Finally, the quadratic curves are fitted as the model of the lines and are projected back to the original image space. Compared with the current other feature-based lane detection algorithms, our algorithm can deal with multi-curve or cross horizontal lines better in the track-following application with better robustness.","PeriodicalId":183887,"journal":{"name":"2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123824077","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
MSAM: A Multi-Layer Bi-LSTM Based Speech to Vector Model with Residual Attention Mechanism 基于残馀注意机制的多层双lstm语音向量模型
2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC) Pub Date : 2019-06-12 DOI: 10.1109/EDSSC.2019.8753946
Dongdong Cui, S. Yin, Jiangyuan Gu, Leibo Liu, Shaojun Wei
{"title":"MSAM: A Multi-Layer Bi-LSTM Based Speech to Vector Model with Residual Attention Mechanism","authors":"Dongdong Cui, S. Yin, Jiangyuan Gu, Leibo Liu, Shaojun Wei","doi":"10.1109/EDSSC.2019.8753946","DOIUrl":"https://doi.org/10.1109/EDSSC.2019.8753946","url":null,"abstract":"Word embedding is one of the most popular representation of a document vocabulary. It is capable of capturing the context, semantic and syntactic similarity of words in a document. Word2vec is a well-known technique to learn word embeddings of fixed dimensionality by using shallow neural networks, which can also be used to transform the audio segment of each words into a vector. In this paper, a deep neural network based on speech to vector model is proposed to learn the vector directly from the speech segment, in which the vector can represent some semantic information. Unlike the previous methods, such as speech2vec [1], our proposed model adopts a high-performance parser based on the residual attention mechanism, which uses multi-layer bi-directional long short-term memory (LSTM) network to learn representations of the audio segment. Finally, our proposed speech to vector model is analyzed and evaluated on 12 public datasets, which are widely-used in word similarity and word analogy benchmarks.","PeriodicalId":183887,"journal":{"name":"2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"123 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115588906","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A Temperature-Compensated Power-on-Reset Circuit in 40nm CMOS 40nm CMOS温度补偿电源复位电路
2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC) Pub Date : 2019-06-12 DOI: 10.1109/EDSSC.2019.8754457
Yanfei Lin, Ken Xu
{"title":"A Temperature-Compensated Power-on-Reset Circuit in 40nm CMOS","authors":"Yanfei Lin, Ken Xu","doi":"10.1109/EDSSC.2019.8754457","DOIUrl":"https://doi.org/10.1109/EDSSC.2019.8754457","url":null,"abstract":"To improve the accuracy and eliminate the bandgap reference circuit of conventional POR (power-on-reset) circuits, a low-cost, low-power, temperature-compensated POR circuit with precise trigger voltage is presented in this paper. The proposed POR circuit was designed and implemented in a 40nm CMOS technology. It achieves a 740nA quiescent current under 1.1V power supply, a 0.008mm2 active area, and a 350ppm/°C trigger voltage temperature coefficient from -40°C to 120°C.","PeriodicalId":183887,"journal":{"name":"2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124141967","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A 16-bit 64-channel ADC without Input Impedance Transformation for Measurement System 一种用于测量系统的无输入阻抗变换的16位64通道ADC
2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC) Pub Date : 2019-06-12 DOI: 10.1109/EDSSC.2019.8754034
Guangyi Chen, Xueyou Shi, Dahe Liu, Wengao Lu, Zhongjian Chen
{"title":"A 16-bit 64-channel ADC without Input Impedance Transformation for Measurement System","authors":"Guangyi Chen, Xueyou Shi, Dahe Liu, Wengao Lu, Zhongjian Chen","doi":"10.1109/EDSSC.2019.8754034","DOIUrl":"https://doi.org/10.1109/EDSSC.2019.8754034","url":null,"abstract":"A multiplexed 16-bit 64-channel ADC for multi-sensors measurement system is presented. In order to directly interface with multi-type sensors without input impedance transformation buffers used in conventional designs. A dual signal-processing path architecture and a data fusion algorithm are utilized in this work for signal conditioning and quantization. Through the above solutions, this ADC saves considerable amount of power consumption and area cost, therefore enables much more channels and easier system integration. A prototype circuit has been designed in 0.18μm CMOS process. Simulation results reveal 98. 2dB total harmonic distortion (THD) and 14.8-bit ENOB with full-scale input at IMSPS.","PeriodicalId":183887,"journal":{"name":"2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"140 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128479036","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Multi-stage Cross-Coupled Amplifier 多级交叉耦合放大器
2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC) Pub Date : 2019-06-12 DOI: 10.1109/EDSSC.2019.8753944
Yuet Ho Woo, Ming Wai Lau, C. H. Hung, Yong Zhou, K. Leung
{"title":"A Multi-stage Cross-Coupled Amplifier","authors":"Yuet Ho Woo, Ming Wai Lau, C. H. Hung, Yong Zhou, K. Leung","doi":"10.1109/EDSSC.2019.8753944","DOIUrl":"https://doi.org/10.1109/EDSSC.2019.8753944","url":null,"abstract":"A multi-stage cross-coupled amplifier (MSCC) is presented. Implemented in a 130-nm CMOS technology, experimental results show that the MSCC amplifier driving a 15-nF load capacitance achieves dc gain of about 80dB, unity gain frequency of 0.398 MHz and phase margin of 75.9°.","PeriodicalId":183887,"journal":{"name":"2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131328405","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design and fabrication of charge-balanced SGRSO MOSFET 电荷平衡SGRSO MOSFET的设计与制造
2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC) Pub Date : 2019-06-12 DOI: 10.1109/EDSSC.2019.8754347
D. Yan, Liu Xin, He Ming, Zhang Yan Fei, Chen Ze, Gong Xue Qin
{"title":"Design and fabrication of charge-balanced SGRSO MOSFET","authors":"D. Yan, Liu Xin, He Ming, Zhang Yan Fei, Chen Ze, Gong Xue Qin","doi":"10.1109/EDSSC.2019.8754347","DOIUrl":"https://doi.org/10.1109/EDSSC.2019.8754347","url":null,"abstract":"The simulation research and process development of Split-Gate Resurf Stepped Oxide (SGRSO) MOSFET are introduced in this paper. The devices are simulated with different epitaxial resistivity, P-body structures, gate structure and gate oxide thickness, etc. The electric field distribution of the device is optimized, and the longitudinal electric field is approximately trapezoidal. A MOSFET with breakdown voltage of 75V, threshold voltage of 1.8V, quality factor FOM of 5.94m$Omega$.nC is obtained. The SGRSO MOSFET is fabricated based on the Integrated Circuit Pilot Process Platform of IMECAS, and packaged with SMD-0.5. The breakdown voltage BVDSS is 76V, and the specific on-resistance Rdson is 0.39m$Omega$/mm2, while the planar gate device of the same voltage level is 2.36m$Omega$/mm$^{2}$.","PeriodicalId":183887,"journal":{"name":"2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123645829","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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