5/ 10gb /s双模NRZ/PAM4 CDR, 65nm CMOS

2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC) Pub Date : 2019-06-12 DOI:10.1109/EDSSC.2019.8754128

Ruichang Ma, Mengdi Cao, Guopei Chen, Luqiang Duan, Zheng Song, B. Chi

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引用次数: 2

摘要

提出了一种基于相位插值器(PI)的65nm CMOS双模时钟和数据恢复(CDR)电路。CDR可以从非至零(NRZ)模式的正交相移键控(QPSK)调制信号和4脉冲调幅(PAM4)模式的16正交调幅(QAM)信号中恢复时钟。提出了一种针对PAM4信号的自适应阈值电压环。仿真结果表明，CDR可以在两种模式下跟踪发送端和接收端之间±1000ppm的最大频偏，锁定时钟的抖动在NRZ模式下为45.2ps，在PAM4模式下为47.8ps。

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A 5/10 Gb/s Dual-Mode NRZ/PAM4 CDR in 65-nm CMOS

A dual-mode clock and data recovery (CDR) circuit based on phase interpolator (PI) in 65nm CMOS is presented. CDR can recover clock from quadrature phase shift keying (QPSK) modulated signal in non-to-zero (NRZ) mode, and 16 quadrature amplitude modulation (QAM) signal in 4 pulse amplitude modulation (PAM4) mode. An adaptive threshold voltage loop for PAM4 signal is proposed. Simulation results show that CDR can track maximum ± 1000 ppm frequency offset between transmitter and receiver in two modes, and the jitter of the locked clock is 45.2ps in NRZ mode and 47.8ps in PAM4 mode, respectively.

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来源期刊

2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)

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