Design and fabrication of charge-balanced SGRSO MOSFET

Abstract

The simulation research and process development of Split-Gate Resurf Stepped Oxide (SGRSO) MOSFET are introduced in this paper. The devices are simulated with different epitaxial resistivity, P-body structures, gate structure and gate oxide thickness, etc. The electric field distribution of the device is optimized, and the longitudinal electric field is approximately trapezoidal. A MOSFET with breakdown voltage of 75V, threshold voltage of 1.8V, quality factor FOM of 5.94m$\Omega$.nC is obtained. The SGRSO MOSFET is fabricated based on the Integrated Circuit Pilot Process Platform of IMECAS, and packaged with SMD-0.5. The breakdown voltage BVDSS is 76V, and the specific on-resistance Rdson is 0.39m$\Omega$/mm2, while the planar gate device of the same voltage level is 2.36m$\Omega$/mm$^{2}$.