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2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)最新文献

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Design and Optimization of an Area-efficient SOT-MRAM 面积高效SOT-MRAM的设计与优化
2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC) Pub Date : 2019-06-12 DOI: 10.1109/EDSSC.2019.8754166
Chao Wang, Zhaohao Wang, Bi Wu, Weisheng Zhao
{"title":"Design and Optimization of an Area-efficient SOT-MRAM","authors":"Chao Wang, Zhaohao Wang, Bi Wu, Weisheng Zhao","doi":"10.1109/EDSSC.2019.8754166","DOIUrl":"https://doi.org/10.1109/EDSSC.2019.8754166","url":null,"abstract":"Spin orbit torque magnetic random access memory (SOT-MRAM) has attracted numerous research interests since it promises to overcome the write speed and energy bottlenecks of the conventional STT-MRAM. However, the cell density of SOT-MRAM is constrained due to more access transistors. In this work, we present a NAND-Like architecture for SOT-MRAM with a single transistor and several diodes, as well as a novel adaptive array design based on the proposed cell structure. Compared with the standard SOTMRAM, the proposed SOT-MRAM achieves significant improvement in the cell density by sharing transistors, meanwhile attains a comparable write speed. The overhead of write energy can be compensated by a well-designed write policy.","PeriodicalId":183887,"journal":{"name":"2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130662353","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A Background Timing Skew Calibration Technique in Time-Interleaved ADCs 时间交错adc的背景时序偏差校准技术
2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC) Pub Date : 2019-06-12 DOI: 10.1109/EDSSC.2019.8754374
Zekai Wu, Fule Li, Meng Ni, Yang Ding, Zhihua Wang
{"title":"A Background Timing Skew Calibration Technique in Time-Interleaved ADCs","authors":"Zekai Wu, Fule Li, Meng Ni, Yang Ding, Zhihua Wang","doi":"10.1109/EDSSC.2019.8754374","DOIUrl":"https://doi.org/10.1109/EDSSC.2019.8754374","url":null,"abstract":"This paper presents a background timing skew calibration technique for time-interleaved analog-to-digital converters(ADCs). The timing skew between two adjacent sub- ADCs is detected in the digital domain through slope-based and statistics-based technique. Based on the detection error, the digitally controlled delay line(DCDL) is driven to minimum the timing skew. Using the proposed calibration algorithm in a 14- bit 500MS/s TI ADC model, the MATLAB simulation result shows a convergence time of 346ms under Nyquist frequency input with 1% oTs initial timing mismatch, and the proposed method can effectively reduce hardware consumption in circuit implementation.","PeriodicalId":183887,"journal":{"name":"2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133184578","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 1.25-8.5 Gb/s wide range CDR with locking detector in 40 nm CMOS technology 采用40纳米CMOS技术，带锁定检测器的1.25-8.5 Gb/s宽范围CDR
2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC) Pub Date : 2019-06-12 DOI: 10.1109/EDSSC.2019.8754203
Wenhuan Luan, Xiangyu Li, Dengjie Wang, Ziqiang Wang, Xin Lin, Mao Li
{"title":"A 1.25-8.5 Gb/s wide range CDR with locking detector in 40 nm CMOS technology","authors":"Wenhuan Luan, Xiangyu Li, Dengjie Wang, Ziqiang Wang, Xin Lin, Mao Li","doi":"10.1109/EDSSC.2019.8754203","DOIUrl":"https://doi.org/10.1109/EDSSC.2019.8754203","url":null,"abstract":"A 1.25-8.5 Gb/s wide range clock and data recovery (CDR) circuit in a multi-protocol SerDes is presented in this paper. The CDR is based on phase interpolator (PI). The local off-chip reference clock is interpolated by the PI to recover the clock at the same frequency as the data rate. Then CDR could retime received data with input jitter and noise in order to export clean waveforms. The circuit is designed in 40nm CMOS technology at 1.1 V supply voltage. Measured results show that bit error rate (BER) is less than 1e-9 and jitter tolerance (JTOL) agrees with template requirements at 1.25-8.5 Gb/s.","PeriodicalId":183887,"journal":{"name":"2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"113 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116666914","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 0.7-V 3.37-MHz-GBW OTA Driving 15 nF With Triple Gm-Boosting Cells 一个0.7 v 3.37 mhz - gbw OTA驱动15 nF与三重gm - boost电池
2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC) Pub Date : 2019-06-12 DOI: 10.1109/EDSSC.2019.8754046
Yuet Ho Woo, Joi Hei Chan, C. H. Hung, K. Leung, Yanqi Zheng, Jianping Guo
{"title":"A 0.7-V 3.37-MHz-GBW OTA Driving 15 nF With Triple Gm-Boosting Cells","authors":"Yuet Ho Woo, Joi Hei Chan, C. H. Hung, K. Leung, Yanqi Zheng, Jianping Guo","doi":"10.1109/EDSSC.2019.8754046","DOIUrl":"https://doi.org/10.1109/EDSSC.2019.8754046","url":null,"abstract":"A proposed cascade structure of triple Gm-boosting cells is proposed and applied to an OTA to enhance voltage gain and gain bandwidth product (GBW) by enhancing small-signal output currents. The proposed OTA is designed in UMC 130-nm CMOS technology. The simulated results with a 15nF load and 0.7 V supply show small-signal figure-of-merit of 260,1300 MHz$cdot$pF/mW.","PeriodicalId":183887,"journal":{"name":"2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115134708","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Statistics-Based Background Timing Skew Calibration Algorithm for Time-Interleaved ADCs 基于统计的时间交错adc背景时序偏差校正算法
2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC) Pub Date : 2019-06-12 DOI: 10.1109/EDSSC.2019.8754134
Yufan Feng, Weixin Gai, Xiaole Cui
{"title":"A Statistics-Based Background Timing Skew Calibration Algorithm for Time-Interleaved ADCs","authors":"Yufan Feng, Weixin Gai, Xiaole Cui","doi":"10.1109/EDSSC.2019.8754134","DOIUrl":"https://doi.org/10.1109/EDSSC.2019.8754134","url":null,"abstract":"A modified statistics-based background calibration algorithm is proposed, which estimates and compensates errors due to the timing skew of time-interleaved ADCs in a digital-mixing way. The mismatch-induced error signal is corrected by calculating the cross-correlation between each sub-ADC and an additional calibration ADC. The output of the supplementary channel is delayed during data processing, different from the conventional statistics-based method that is susceptible to quantization noise. Simulation results of an 8-bit 2-GS/s four-channel time-interleaved ADC behavioral model show that the proposed method is effective and efficient.","PeriodicalId":183887,"journal":{"name":"2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"417 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122198712","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 16-phase 8-branch Charge Pump With Advanced Charge Recycling Strategy 具有先进电荷回收策略的16相8分支电荷泵
2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC) Pub Date : 2019-06-12 DOI: 10.1109/EDSSC.2019.8753947
Hui Peng, P. Bauwens, H. Pauw, J. Doutreloigne
{"title":"A 16-phase 8-branch Charge Pump With Advanced Charge Recycling Strategy","authors":"Hui Peng, P. Bauwens, H. Pauw, J. Doutreloigne","doi":"10.1109/EDSSC.2019.8753947","DOIUrl":"https://doi.org/10.1109/EDSSC.2019.8753947","url":null,"abstract":"4-phase 2-branch and 16-phase 8-branch charge pumps are proposed to decrease the power dissipation due to parasitic capacitance. By using the charge recycling concept, the power efficiency is increased about 55% and 88% respectively compared to a traditional Dickson charge pump. The proposed multi-branch charge pumps can also significantly reduce the output voltage ripple.","PeriodicalId":183887,"journal":{"name":"2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116441879","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A Highly Linear Low Power Envelope Detector 一种高线性低功率包络检测器
2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC) Pub Date : 2019-06-12 DOI: 10.1109/EDSSC.2019.8754090
Yi Su, Qin Xia, Li Geng, Xin-Ke Liu
{"title":"A Highly Linear Low Power Envelope Detector","authors":"Yi Su, Qin Xia, Li Geng, Xin-Ke Liu","doi":"10.1109/EDSSC.2019.8754090","DOIUrl":"https://doi.org/10.1109/EDSSC.2019.8754090","url":null,"abstract":"This paper presents a direct voltage detection architecture that can be used for linear envelope detectors. A preamplifier using a common-gate (CG) common-source (CS) circuit topology sends the input modulated signal to a differential output and is coupled to a pair of common source stages. By using the quadratic IV curve of the MOSFETs, the detector can achieve linear operations on the detected envelope signals. The envelope detector was designed using a standard 0.18 $mu n$ CMOS process. The simulation result shows the detector can track a 120 MHz modulation signal at cost of 18 mW of static power with a 1.8 V power supply.","PeriodicalId":183887,"journal":{"name":"2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133085702","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A DEM-Free Sturdy MASH Delta-Sigma Modulator with a Highly-Linear Tri-level DAC 具有高线性三电平DAC的无dem坚固MASH Delta-Sigma调制器
2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC) Pub Date : 2019-06-12 DOI: 10.1109/EDSSC.2019.8754500
W. Jin, K. Pun
{"title":"A DEM-Free Sturdy MASH Delta-Sigma Modulator with a Highly-Linear Tri-level DAC","authors":"W. Jin, K. Pun","doi":"10.1109/EDSSC.2019.8754500","DOIUrl":"https://doi.org/10.1109/EDSSC.2019.8754500","url":null,"abstract":"Multi-stage noise shaping (MASH) Delta-Sigma modulators (DSMs) can achieve high-order noise shaping with single-bit quantizers, but they require high opamp gain for precise matching between the analog and the digital filters. The Sturdy MASH (SMASH) DSM relaxes the opamp gain requirement but multi-bit digital-to-analog converters (DACs) become necessary. The SMASH structure thus loses the inherent linearity arisen from the 1-bit DACs in the MASH structure, and often employ a dynamic element matching (DEM) scheme, which imposes a speed limit to the modulator. This work presents a DEM-free SMASH DSM by employing an inherently linear 3-level DAC in the first stage, which combines the advantages of both the MASH and SMASH structures. Simulations results are presented, validating the proposed architecture.","PeriodicalId":183887,"journal":{"name":"2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134397638","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 12-bit 200MS/s Pipelined-SAR ADC in 65-nm CMOS with 61.9 dB SNDR 12位200MS/s流水线sar ADC, 65nm CMOS, SNDR为61.9 dB
2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC) Pub Date : 2019-06-12 DOI: 10.1109/EDSSC.2019.8754022
Haizhu Liu, Maliang Liu, Zhangming Zhu
{"title":"A 12-bit 200MS/s Pipelined-SAR ADC in 65-nm CMOS with 61.9 dB SNDR","authors":"Haizhu Liu, Maliang Liu, Zhangming Zhu","doi":"10.1109/EDSSC.2019.8754022","DOIUrl":"https://doi.org/10.1109/EDSSC.2019.8754022","url":null,"abstract":"This paper presents a 12-bit 200MS/s Pipelined-SAR hybrid architecture ADC with a 3.5-bit MDAC for the first stage and a 9-bit SAR ADC for the second stage. In the MDAC, a low-power high DC-gain class-AB residue amplifier is proposed to achieve 80dB DC-gain and 0.8GHz unity-gain-bandwidth (UGB). In the SAR ADC, two techniques are applied to accelerate the comparison speed to meet the requirement of high-speed ADC. Fabricated in a 65nm CMOS process, the ADC occupies an area of 0.21 mm2 and consumes a power of 7.3 mW. The measured Nyquist SFDR and SNDR are 71.2 dB and 61.9 dB at 200 MS/s. The ADC achieves a FoM of 35.6 fJ/conversion-step.","PeriodicalId":183887,"journal":{"name":"2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"169 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132276738","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
An Analytical Model for Hybrid Multiple-Gate (HMG) Tunnel FET 混合多栅(HMG)隧道场效应管的解析模型
2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC) Pub Date : 2019-06-12 DOI: 10.1109/EDSSC.2019.8753954
Yu-Hsuan Lin, Chia-Ling Young, Shi Su, T. Chiang
{"title":"An Analytical Model for Hybrid Multiple-Gate (HMG) Tunnel FET","authors":"Yu-Hsuan Lin, Chia-Ling Young, Shi Su, T. Chiang","doi":"10.1109/EDSSC.2019.8753954","DOIUrl":"https://doi.org/10.1109/EDSSC.2019.8753954","url":null,"abstract":"Based on the quasi-3D/quasi-2D scaling theory, quasi-3D/quasi-2D potential approach, WKB approximation and Kane’s model, a new analytical model including the channel potential, on/off drain current, and threshold voltage is developed for the hybrid multiple-gate (HMG) tunnel FET (TFET) with a small scaling length $(lambda sRG)$ of surrounding-gate (SRG) TEFT near the source side and a large scaling length $(lambda_{DG)}$ of double-gate (DG) TEFT near the drain side. It is found that with the HMG structure, the tunnel path caused by $lambda sRG$ in the source-channel region can be effectively decreased, which hence enhances the on-state current. Besides, the off-state current can be efficiently suppressed by the HMG structure due to long tunnel path induced by $lambda_{DG}$ in the drain-channel region.","PeriodicalId":183887,"journal":{"name":"2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114774036","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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