{"title":"An Analytical Model for Hybrid Multiple-Gate (HMG) Tunnel FET","authors":"Yu-Hsuan Lin, Chia-Ling Young, Shi Su, T. Chiang","doi":"10.1109/EDSSC.2019.8753954","DOIUrl":null,"url":null,"abstract":"Based on the quasi-3D/quasi-2D scaling theory, quasi-3D/quasi-2D potential approach, WKB approximation and Kane’s model, a new analytical model including the channel potential, on/off drain current, and threshold voltage is developed for the hybrid multiple-gate (HMG) tunnel FET (TFET) with a small scaling length $(\\lambda sRG)$ of surrounding-gate (SRG) TEFT near the source side and a large scaling length $(\\lambda_{DG)}$ of double-gate (DG) TEFT near the drain side. It is found that with the HMG structure, the tunnel path caused by $\\lambda sRG$ in the source-channel region can be effectively decreased, which hence enhances the on-state current. Besides, the off-state current can be efficiently suppressed by the HMG structure due to long tunnel path induced by $\\lambda_{DG}$ in the drain-channel region.","PeriodicalId":183887,"journal":{"name":"2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EDSSC.2019.8753954","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
Based on the quasi-3D/quasi-2D scaling theory, quasi-3D/quasi-2D potential approach, WKB approximation and Kane’s model, a new analytical model including the channel potential, on/off drain current, and threshold voltage is developed for the hybrid multiple-gate (HMG) tunnel FET (TFET) with a small scaling length $(\lambda sRG)$ of surrounding-gate (SRG) TEFT near the source side and a large scaling length $(\lambda_{DG)}$ of double-gate (DG) TEFT near the drain side. It is found that with the HMG structure, the tunnel path caused by $\lambda sRG$ in the source-channel region can be effectively decreased, which hence enhances the on-state current. Besides, the off-state current can be efficiently suppressed by the HMG structure due to long tunnel path induced by $\lambda_{DG}$ in the drain-channel region.