D. Yan, Liu Xin, He Ming, Zhang Yan Fei, Chen Ze, Gong Xue Qin
{"title":"电荷平衡SGRSO MOSFET的设计与制造","authors":"D. Yan, Liu Xin, He Ming, Zhang Yan Fei, Chen Ze, Gong Xue Qin","doi":"10.1109/EDSSC.2019.8754347","DOIUrl":null,"url":null,"abstract":"The simulation research and process development of Split-Gate Resurf Stepped Oxide (SGRSO) MOSFET are introduced in this paper. The devices are simulated with different epitaxial resistivity, P-body structures, gate structure and gate oxide thickness, etc. The electric field distribution of the device is optimized, and the longitudinal electric field is approximately trapezoidal. A MOSFET with breakdown voltage of 75V, threshold voltage of 1.8V, quality factor FOM of 5.94m$\\Omega$.nC is obtained. The SGRSO MOSFET is fabricated based on the Integrated Circuit Pilot Process Platform of IMECAS, and packaged with SMD-0.5. The breakdown voltage BVDSS is 76V, and the specific on-resistance Rdson is 0.39m$\\Omega$/mm2, while the planar gate device of the same voltage level is 2.36m$\\Omega$/mm$^{2}$.","PeriodicalId":183887,"journal":{"name":"2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Design and fabrication of charge-balanced SGRSO MOSFET\",\"authors\":\"D. Yan, Liu Xin, He Ming, Zhang Yan Fei, Chen Ze, Gong Xue Qin\",\"doi\":\"10.1109/EDSSC.2019.8754347\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The simulation research and process development of Split-Gate Resurf Stepped Oxide (SGRSO) MOSFET are introduced in this paper. The devices are simulated with different epitaxial resistivity, P-body structures, gate structure and gate oxide thickness, etc. The electric field distribution of the device is optimized, and the longitudinal electric field is approximately trapezoidal. A MOSFET with breakdown voltage of 75V, threshold voltage of 1.8V, quality factor FOM of 5.94m$\\\\Omega$.nC is obtained. The SGRSO MOSFET is fabricated based on the Integrated Circuit Pilot Process Platform of IMECAS, and packaged with SMD-0.5. The breakdown voltage BVDSS is 76V, and the specific on-resistance Rdson is 0.39m$\\\\Omega$/mm2, while the planar gate device of the same voltage level is 2.36m$\\\\Omega$/mm$^{2}$.\",\"PeriodicalId\":183887,\"journal\":{\"name\":\"2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)\",\"volume\":\"58 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-06-12\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EDSSC.2019.8754347\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EDSSC.2019.8754347","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design and fabrication of charge-balanced SGRSO MOSFET
The simulation research and process development of Split-Gate Resurf Stepped Oxide (SGRSO) MOSFET are introduced in this paper. The devices are simulated with different epitaxial resistivity, P-body structures, gate structure and gate oxide thickness, etc. The electric field distribution of the device is optimized, and the longitudinal electric field is approximately trapezoidal. A MOSFET with breakdown voltage of 75V, threshold voltage of 1.8V, quality factor FOM of 5.94m$\Omega$.nC is obtained. The SGRSO MOSFET is fabricated based on the Integrated Circuit Pilot Process Platform of IMECAS, and packaged with SMD-0.5. The breakdown voltage BVDSS is 76V, and the specific on-resistance Rdson is 0.39m$\Omega$/mm2, while the planar gate device of the same voltage level is 2.36m$\Omega$/mm$^{2}$.
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