{"title":"一种基于推挽缓冲器的快速瞬态响应无电容LDO","authors":"Qiang Li, Kai Wang, Jian-jun Zhao","doi":"10.1109/EDSSC.2019.8753937","DOIUrl":null,"url":null,"abstract":"This paper presents a fast transient capacitor-less low-dropout regulator (LDO). A Push-Pull Buffer (PPB) is proposed to drive the pass transistor. The low output resistance of the PPB allows the pole at the gate of the pass transistor to be pushed beyond the unity-gain frequency of the LDO regulation loop. Transient response is improved, the settling time of LDO are $0.2\\mu \\mathrm{S}\\text{@} \\mathrm{C}_{\\mathrm{L}}=0\\mathrm{p}$F and $1.14\\mu \\mathrm{S}\\text{@}\\mathrm{C}_{\\mathrm{L}}=100\\mathrm{p}$F. The input transistors of error amplifier are realized Cascode structure which is used for connecting compensation capacitor Cc. With this structure, RHP zero generated by compensation capacitor is pushed beyond the unity-gain frequency of the LDO regulation loop. And LHP zero generated by the Cc is used to compensate the non-dominate poles. Compensation capacitance is 1pF. The Dynamic Transient Improvement (DTI) circuit is adopted to reduce the ripples of the output voltage of LDO. The proposed LDO can operate from a supply voltage of 2.2V-4V with a minimum dropout voltage of 0. 2V at a maximum 50mA load and quiescent current of 70$\\mu$A. Only 4pF capacitor is integrated in the chip, the output of LDO can be connected 0- 100pF off-chip capacitor.","PeriodicalId":183887,"journal":{"name":"2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"215 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"A Capacitor-less LDO with Fast transient response using Push-Pull Buffer\",\"authors\":\"Qiang Li, Kai Wang, Jian-jun Zhao\",\"doi\":\"10.1109/EDSSC.2019.8753937\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a fast transient capacitor-less low-dropout regulator (LDO). A Push-Pull Buffer (PPB) is proposed to drive the pass transistor. The low output resistance of the PPB allows the pole at the gate of the pass transistor to be pushed beyond the unity-gain frequency of the LDO regulation loop. Transient response is improved, the settling time of LDO are $0.2\\\\mu \\\\mathrm{S}\\\\text{@} \\\\mathrm{C}_{\\\\mathrm{L}}=0\\\\mathrm{p}$F and $1.14\\\\mu \\\\mathrm{S}\\\\text{@}\\\\mathrm{C}_{\\\\mathrm{L}}=100\\\\mathrm{p}$F. The input transistors of error amplifier are realized Cascode structure which is used for connecting compensation capacitor Cc. With this structure, RHP zero generated by compensation capacitor is pushed beyond the unity-gain frequency of the LDO regulation loop. And LHP zero generated by the Cc is used to compensate the non-dominate poles. Compensation capacitance is 1pF. The Dynamic Transient Improvement (DTI) circuit is adopted to reduce the ripples of the output voltage of LDO. The proposed LDO can operate from a supply voltage of 2.2V-4V with a minimum dropout voltage of 0. 2V at a maximum 50mA load and quiescent current of 70$\\\\mu$A. Only 4pF capacitor is integrated in the chip, the output of LDO can be connected 0- 100pF off-chip capacitor.\",\"PeriodicalId\":183887,\"journal\":{\"name\":\"2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)\",\"volume\":\"215 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-06-12\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EDSSC.2019.8753937\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EDSSC.2019.8753937","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A Capacitor-less LDO with Fast transient response using Push-Pull Buffer
This paper presents a fast transient capacitor-less low-dropout regulator (LDO). A Push-Pull Buffer (PPB) is proposed to drive the pass transistor. The low output resistance of the PPB allows the pole at the gate of the pass transistor to be pushed beyond the unity-gain frequency of the LDO regulation loop. Transient response is improved, the settling time of LDO are $0.2\mu \mathrm{S}\text{@} \mathrm{C}_{\mathrm{L}}=0\mathrm{p}$F and $1.14\mu \mathrm{S}\text{@}\mathrm{C}_{\mathrm{L}}=100\mathrm{p}$F. The input transistors of error amplifier are realized Cascode structure which is used for connecting compensation capacitor Cc. With this structure, RHP zero generated by compensation capacitor is pushed beyond the unity-gain frequency of the LDO regulation loop. And LHP zero generated by the Cc is used to compensate the non-dominate poles. Compensation capacitance is 1pF. The Dynamic Transient Improvement (DTI) circuit is adopted to reduce the ripples of the output voltage of LDO. The proposed LDO can operate from a supply voltage of 2.2V-4V with a minimum dropout voltage of 0. 2V at a maximum 50mA load and quiescent current of 70$\mu$A. Only 4pF capacitor is integrated in the chip, the output of LDO can be connected 0- 100pF off-chip capacitor.