2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD)最新文献_第5页

Using LV process to design high voltage DDDMOSFET and LDMOSFET with 3-D profile structure 采用低压工艺设计了具有三维轮廓结构的高压DDDMOSFET和LDMOSFET

2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD) Pub Date : 2013-05-26 DOI: 10.1109/ISPSD.2013.6694463

Chien-Hao Huang, Tsung-Yi Huang, C. Yang, H. Chu, K. Lo, C. Hung, Kuo-Cheng Chang, H. Su, Chih-Fang Huang, J. Gong

引用次数: 1

MHz-converter design for high conversion ratio 高转换率的mhz变换器设计

2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD) Pub Date : 2013-05-26 DOI: 10.1109/ISPSD.2013.6694445

J. Wittmann, B. Wicht

{"title":"MHz-converter design for high conversion ratio","authors":"J. Wittmann, B. Wicht","doi":"10.1109/ISPSD.2013.6694445","DOIUrl":"https://doi.org/10.1109/ISPSD.2013.6694445","url":null,"abstract":"This paper presents a circuit design and efficiency study for integrated converters with switching frequencies up to 15 MHz at high conversion ratio with input voltages up to 40 V and output voltages <;5 V. An asynchronous buck converter is well suitable, while in contrast, a synchronous topology causes larger switching losses due to its low side switch. Critical design aspects are presented along with an implementation in a 180 nm HV BiCMOS technology. A saw-tooth with fast fall time is achieved with two interleaved integrator stages. The limitation due to the finite fall-time of the saw tooth signal was solved by a PWM comparator that gets reset by a synchronized clock with an adjusted lead time at min. or max. duty cycle, respectively. A high speed level shifter is used to shift the PWM signal to the high side domain. The gate driver uses a two-branch tapered buffer with asymmetry factor to achieve maximum switching speed while at the same time the current consumption is minimized. An efficiency model, verified by measurements, allows to simulate and to determine quantitatively the root cause of the power losses separately for each circuit block. At 15 MHz and 10 V input voltage a peak efficiency of ~65% was achieved. While the efficiency reduces to about 35% for a conversion from 40 V input to 5 V output, resonant concepts are expected to reach >50% efficiency. In experiments a switching frequency of 40 MHz was achieved.","PeriodicalId":175520,"journal":{"name":"2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132210588","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 17

Ultralow on-resistance 30–40 V UMOSFET by 2-D scaling of ion-implanted superjunction structure 基于离子注入超结结构的30-40 V超低导通电阻UMOSFET

2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD) Pub Date : 2013-05-26 DOI: 10.1109/ISPSD.2013.6694403

Hisanori Okubo, Kenya Kobayashi, Y. Kawashima

引用次数: 8

Low voltage MOSFET optimized for low VDS transient voltages 针对低VDS瞬态电压优化的低压MOSFET

2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD) Pub Date : 2013-05-26 DOI: 10.1109/ISPSD.2013.6694402

P. Rutter, S. Peake, A. Elford

引用次数: 6

0.35μm, 30V fully isolated and low-Ron nLDMOS for DC-DC applications 0.35μm, 30V完全隔离和低ron nLDMOS，用于DC-DC应用

2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD) Pub Date : 2013-05-26 DOI: 10.1109/ISPSD.2013.6694454

Kyungho Lee, Haeung Jeon, Byunghee Cho, Joonhee Cho, Yon-Sup Pang, Jin-Seok Moon, S. Kwon, F. Hébert, Junghwan Lee, Taejong Lee

引用次数: 17

60V-class power IC technology for an intelligent power switch with an integrated trench MOSFET 60v级功率IC技术，用于集成沟槽MOSFET的智能电源开关

2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD) Pub Date : 2013-05-26 DOI: 10.1109/ISPSD.2013.6694450

Y. Toyoda, Hideaki Katakura, Takatoshi Ooe, M. Iwaya, H. Sumida

引用次数: 3

Comparison of theoretical limits between superjunction and field plate structures 超结结构与场极板结构的理论极限比较

2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD) Pub Date : 2013-05-26 DOI: 10.1109/ISPSD.2013.6694461

W. Saito

引用次数: 32

A novel high voltage Pch-MOS with a new drain drift structure for 1200V HVICs 一种用于1200V hvic的新型漏极漂移结构的高压Pch-MOS

2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD) Pub Date : 2013-05-26 DOI: 10.1109/ISPSD.2013.6694401

M. Yoshino, K. Shimizu

引用次数: 6

A novel super-junction trench gate MOSFET fabricated using high aspect-ratio trench etching and boron lateral diffusion technologies 采用高宽高比沟槽刻蚀和硼横向扩散技术制备了一种新型的超结沟槽栅MOSFET

2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD) Pub Date : 2013-05-26 DOI: 10.1109/ISPSD.2013.6694459

S. G. Kim, H. Park, S. Yoo, K. Na, J. Koo, J. Won, K. Park, Y. Yang, J. Lee

{"title":"A novel super-junction trench gate MOSFET fabricated using high aspect-ratio trench etching and boron lateral diffusion technologies","authors":"S. G. Kim, H. Park, S. Yoo, K. Na, J. Koo, J. Won, K. Park, Y. Yang, J. Lee","doi":"10.1109/ISPSD.2013.6694459","DOIUrl":"https://doi.org/10.1109/ISPSD.2013.6694459","url":null,"abstract":"We propose a super-junction trench gate MOSFET (SJ TGMOSFET) which is fabricated with a simple p-pillar forming process using deep trench and boron silicate glass (BSG) doping process technologies to reduce the process complexity. The p-pillar region is formed through lateral boron diffusion from BSG film and annealing process after the silicon deep etching. For the SJ TGMOSFET fabricated with BSG lateral diffusion, the controls of the boron concentration and the profile are important to achieve the charge balance between p-and n-pillars. Throughout the various boron doping experiments as well as process simulation, we optimize process conditions related with p-pillar depth, BSG doping concentration and diffusion temperature. Due to the trenched p-pillar, the potential of the SJ TGMOSFET more uniformly distributes and widely spreads into the bulk region of the n-drift layer comparing to the conventional TGMOSFET. The measured breakdown voltage of SJ TGMOSFET increases at least 28% than that of the conventional TGMOSFET.","PeriodicalId":175520,"journal":{"name":"2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127241520","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Intermediate bus architectures: A practical review 中间总线体系结构:实用回顾

2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD) Pub Date : 2013-05-26 DOI: 10.1109/ISPSD.2013.6694471

Don Tan

引用次数: 8