2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD)最新文献_第4页

Integrated 85V rated complimentary LDMOS devices utilizing patterned field plate structures for best-in-class performance in network communication applications 集成85V额定的免费LDMOS器件，利用图案场板结构，在网络通信应用中具有一流的性能

2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD) Pub Date : 2013-05-26 DOI: 10.1109/ISPSD.2013.6694423

Santosh K. Sharma, Yun Shi, M. Zierak, D. Cook, R. Phelps, T. Letavic, N. Feilchenfeld

{"title":"Integrated 85V rated complimentary LDMOS devices utilizing patterned field plate structures for best-in-class performance in network communication applications","authors":"Santosh K. Sharma, Yun Shi, M. Zierak, D. Cook, R. Phelps, T. Letavic, N. Feilchenfeld","doi":"10.1109/ISPSD.2013.6694423","DOIUrl":"https://doi.org/10.1109/ISPSD.2013.6694423","url":null,"abstract":"This paper presents complimentary 85V-rated LDMOS devices integrated in a 180nm power management technology platform. The devices are fabricated using a design technique which utilizes tapered dielectric regions in combination with patterned floating field plated structures. The performance of the new structures are compared to conventional LDMOS structures and it shown that the floating field plated structures have superior BVds-Ron, sp, HCI reliability, and forward safe operating area figures-of-merit. These devices exhibit best-in-class BVds-Ron, sp figure-of-merit (NLDMOS : BVds=130V/Ron, sp=195mΩ.mm2 and PLDMOS : BVds=140V/Ron, sp=530mΩ.mm2) and hot carrier reliability in excess of 10 years analog lifetime for rated VDS = 85V and full range of VGS. These devices enable cost effective integration of PoE systems with multiple interface channels and auxiliary switching regulators.","PeriodicalId":175520,"journal":{"name":"2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","volume":"229 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116446158","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

10 kV SiC BJTs — Static, switching and reliability characteristics 10kv SiC bjt。静态、开关和可靠性特性

2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD) Pub Date : 2013-05-26 DOI: 10.1109/ISPSD.2013.6694409

S. Sundaresan, Stoyan Jeliazkov, B. Grummel, R. Singh

{"title":"10 kV SiC BJTs — Static, switching and reliability characteristics","authors":"S. Sundaresan, Stoyan Jeliazkov, B. Grummel, R. Singh","doi":"10.1109/ISPSD.2013.6694409","DOIUrl":"https://doi.org/10.1109/ISPSD.2013.6694409","url":null,"abstract":"Open-base breakdown voltages as high as 10.5 kV (91% of theoretical avalanche limit and 125 V/μm), on-resistance of 110 mΩ-cm2 close to the unipolar limit of 94 mΩ-cm2, and current gain as high as 75 are measured on 10 kV-class SiC BJTs. Monolithic Darlington-connected BJTs fabricated on the same wafer yield current gains as high as 3400, and show Si BJT-like output characteristics with a differential on-resistance as low as 44 mΩ-cm2 in the saturation region and a distinct quasi-saturation region. Switching measurements performed at a DC link voltage of 5 kV and collector current of 8 A feature a collector current rise time as low as 30 ns during turn-on and collector voltage recovery time as low as 100 ns during turn-off. Very low turn-on and turn-off switching energies of 4.2 mJ and 1.6 mJ, respectively, are extracted from the switching transients, which are 19 and 25 times smaller than the corresponding switching energies reported on 6.5 kV Si IGBTs. When turnedon to a short-circuited load at a collector bias of 4500 V, the 10 kV BJT shows a temperature-invariant, withstand time in excess of 20 μs. Leakage currents <; 1μA (system limit) are measured, even after 234 hours of operation under a DC collector bias of 5000 V at elevated temperatures.","PeriodicalId":175520,"journal":{"name":"2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132409297","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 21

New concept high-voltage IGBT gate driver with self-adjusting active gate control function for SiC-SBD hybrid module 用于SiC-SBD混合模块的具有自调节有源栅极控制功能的新概念高压IGBT栅极驱动器

2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD) Pub Date : 2013-05-26 DOI: 10.1109/ISPSD.2013.6694418

Kohei Onda, A. Konno, J. Sakano

引用次数: 15

Breakthrough in trade-off between threshold voltage and specific on-resistance of SiC-MOSFETs sic - mosfet的阈值电压与导通电阻权衡的突破

2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD) Pub Date : 2013-05-26 DOI: 10.1109/ISPSD.2013.6694397

M. Furuhashi, T. Tanioka, Y. Ebiike, E. Suekawa, Y. Tarui, S. Sakai, N. Yutani, N. Miura, M. Imaizumi, S. Yamakawa, T. Oomori

引用次数: 7

Correlation between MR-DCIV current and high-voltage-stress-induced degradation in LDMOSFETs ldmosfet中MR-DCIV电流与高压应力诱导降解的相关性

2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD) Pub Date : 2013-05-26 DOI: 10.1109/ISPSD.2013.6694426

Yandong He, Lin Han, Ganggang Zhang, Xing Zhang

引用次数: 3

Design and optimization of 700V HVIC technology with multi-ring isolation structure 多环隔离700V HVIC技术的设计与优化

2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD) Pub Date : 2013-05-26 DOI: 10.1109/ISPSD.2013.6694451

Nam-Chil Moon, K. Kwon, Changjun Lee, K. Sung, Bum-Seok Kim, K. Yoo, H. Park

{"title":"Design and optimization of 700V HVIC technology with multi-ring isolation structure","authors":"Nam-Chil Moon, K. Kwon, Changjun Lee, K. Sung, Bum-Seok Kim, K. Yoo, H. Park","doi":"10.1109/ISPSD.2013.6694451","DOIUrl":"https://doi.org/10.1109/ISPSD.2013.6694451","url":null,"abstract":"For high side gate driver IC, we applied to single p-type isolation technic between high side region and 700V LDMOS (lateral double-diffused MOS) drain to reduce electric potential of junction termination by the crossing drain metal of 700V LDMOS. This single p-type isolation has low doping concentration to be fully depleted for maintaining a high voltage, normally more than 700V. It is limited to remove the cross-talk problem caused by leakage current between high side region and drain of 700V LDMOS in HVIC (High Voltage Integrated Circuits) using self-shielding structure. So, we are proposed to multi-ring p-type isolation technic to clear leakage issue between two LDMOS used as level shifters. And a robust high side gate driver IC adapting new self-shielding concept with perfect isolation using p-type multi-ring structure is experimentally realized. Experiment results have shown that over 850V breakdown voltage and no leakage current between LDMOS drain and high side region even though the drain voltage of LDMOS is lower than 2V. In addition, highly doped n+ buried layer in the high side region of proposed structure led good dV/dt immunity.","PeriodicalId":175520,"journal":{"name":"2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124280642","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

A novel 4H-SiC Trench MOS Barrier Schottky rectifier fabricated by a two-mask process 采用双掩膜工艺制备的新型4H-SiC沟槽MOS势垒肖特基整流器

2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD) Pub Date : 2013-05-26 DOI: 10.1109/ISPSD.2013.6694473

Chwan-Ying Lee, C. Yen, K. Chu, Young-Shying Chen, C. Hung, L. Lee, Tzu-Ming Yang, C. Chuang, C. Huang, M. Tsai

引用次数: 9

Suppressing channel-conduction during dynamic avalanche to improve high density power MOSFET ruggedness and reverse recovery softness 抑制动态雪崩时的通道传导，以提高高密度功率MOSFET的坚固性和反向恢复柔软性

2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD) Pub Date : 2013-05-26 DOI: 10.1109/ISPSD.2013.6694413

Jingjing Chen, L. Radic, T. Henson

引用次数: 7

High breakdown voltage AlGaN/GaN MOS-HEMTs-on-Si with atomic-layer-deposited Al2O3 gate insulator 具有原子层沉积Al2O3栅极绝缘体的高击穿电压AlGaN/GaN MOS-HEMTs-on-Si

2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD) Pub Date : 2013-05-26 DOI: 10.1109/ISPSD.2013.6694482

Young-shil Kim, M. Ha, O. Seok, W. Ahn, M. Han

{"title":"High breakdown voltage AlGaN/GaN MOS-HEMTs-on-Si with atomic-layer-deposited Al2O3 gate insulator","authors":"Young-shil Kim, M. Ha, O. Seok, W. Ahn, M. Han","doi":"10.1109/ISPSD.2013.6694482","DOIUrl":"https://doi.org/10.1109/ISPSD.2013.6694482","url":null,"abstract":"We have proposed and fabricated AlGaN/GaN MOSHEMTs employing an atomic-layer-deposited (ALD) Al2O3 gate insulator. A 10-nmm Al2O3 served as passivation layer as well as gate dielectric, which results in stable blocking characteristics. The drain leakage current of the proposed device was decreased by five orders. The leakage current of the conventional device (MESFET) with LGD of 15 μm was 87 μA/mm while that of the proposed device with the same LGD was 0.2 nA/mm. The ratio of the gate leakage current to the total leakage (IG/IDSS) was decreased to 0.1 while that of the conventional one was over 0.8. It was found that ALD-Al2O3 gate insulator made a significant contribution to the device blocking capability by suppressing gate leakage effectively. The measured breakdown voltage (VBR) of the MOSHEMTs with LGD of 20 μm was 1980 V while the VBR of the conventional HEMTs device with the same LGD was 1310 V. In addition, the MOS-HEMTs with 3-μm gate exhibited good dc and pulse characteristics due to passivation effect of the ALD-Al2O3 gate insulator.","PeriodicalId":175520,"journal":{"name":"2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132861829","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

High breakdown voltage InAlN/AlN/GaN HEMTs achieved by Schottky-Source technology 肖特基源技术实现高击穿电压InAlN/AlN/GaN hemt

2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD) Pub Date : 2013-05-26 DOI: 10.1109/ISPSD.2013.6694479

Qi Zhou, Wanjun Chen, Sheng-gen Liu, Bo Zhang, Zhihong Feng, S. Cai, K. J. Chen

引用次数: 4