ldmosfet中MR-DCIV电流与高压应力诱导降解的相关性

2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD) Pub Date : 2013-05-26 DOI:10.1109/ISPSD.2013.6694426

Yandong He, Lin Han, Ganggang Zhang, Xing Zhang

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引用次数: 3

摘要

MR-DCIV电流已经证明了在高压LDMOSFET中沿通道、积累和STI区域描绘界面状态的无损能力。研究了高电压应力下ldmosfet中界面态与MR-DCIV电流的关系。我们的研究结果表明，RON的退化主要受STI区域中新生成的界面态的影响。与具有较高栅极电压的PBTI相比，具有较高漏极电压的关闭状态应力将成为基于sti的nldmosfet的最坏退化条件。

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Correlation between MR-DCIV current and high-voltage-stress-induced degradation in LDMOSFETs

MR-DCIV current has demonstrated the nondestructive capability to profile the interface states along the channel, accumulation and STI regions in high-voltage LDMOSFET. The correlation between interface state and MR-DCIV current has been studied under high voltage stresses in LDMOSFETs. Our study results show that RON degradation is mainly affected by newly-generated interface states in the STI region. Compare to the PBTI with higher gate voltage, OFF-state stress with higher drain voltage would become the worst degradation condition in an STI-based nLDMOSFETs.

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2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD)

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