Chien-Hao Huang, Tsung-Yi Huang, C. Yang, H. Chu, K. Lo, C. Hung, Kuo-Cheng Chang, H. Su, Chih-Fang Huang, J. Gong
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Using LV process to design high voltage DDDMOSFET and LDMOSFET with 3-D profile structure
In this work, layout skills using three dimensional (3D) fish bone, slot, and island patterns to enhance the breakdown voltage of PW/NW junction of lateral MOSFETs is developed. Novel lateral double diffused MOSFETs (LDMOSFET) and Double Diffused Drain MOSFETs (DDDMOSFET) without any high voltage (HV) layer are achieved in a standard 5V low voltage (LV) CMOS technology. From the experiment results, the developed DDDMOSFETs and LDMOSFETs can be used for 10V and 60V application respectively.