2016 IEEE International Reliability Physics Symposium (IRPS)最新文献_第7页

Nanoscale evidence for the superior reliability of SiGe high-k pMOSFETs SiGe高k pmosfet优异可靠性的纳米尺度证据

2016 IEEE International Reliability Physics Symposium (IRPS) Pub Date : 2016-04-17 DOI: 10.1109/IRPS.2016.7574644

M. Waltl, A. Grill, G. Rzepa, W. Goes, J. Franco, B. Kaczer, J. Mitard, T. Grasser

{"title":"Nanoscale evidence for the superior reliability of SiGe high-k pMOSFETs","authors":"M. Waltl, A. Grill, G. Rzepa, W. Goes, J. Franco, B. Kaczer, J. Mitard, T. Grasser","doi":"10.1109/IRPS.2016.7574644","DOIUrl":"https://doi.org/10.1109/IRPS.2016.7574644","url":null,"abstract":"It is commonly accepted that the susceptibility of conventional Si channel pMOSFETs to the negative bias temperature instability (NBTI) is a serious threat to further scaling. One possible solution of this problem is the use of SiGe quantum-well devices, which not only offer high mobilities but also superior NBTI reliability compared to conventional silicon transistors. It has been speculated that the latter is due to the energetically higher valence band edge of the SiGe channel with respect to Si, which increases the energetic separation between the defect bands in the high-k gate stack and the channel. We investigate this claim by comparing the behavior of single-defects in nanoscale devices to the averaged behavior of the large number of defects visible in large-area devices. Using detailed TCAD simulations together with the four-state non-radiative multiphonon model we determine the energetic and spatial locations of the traps in the gate stack and confirm that the previously developed picture correctly explains the significant reliability benefits of SiGe channel devices.","PeriodicalId":172129,"journal":{"name":"2016 IEEE International Reliability Physics Symposium (IRPS)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127338892","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Root cause of degradation in novel HfO2-based ferroelectric memories 新型hfo2基铁电存储器退化的根本原因

2016 IEEE International Reliability Physics Symposium (IRPS) Pub Date : 2016-04-17 DOI: 10.1109/IRPS.2016.7574619

M. Pešić, F. Fengler, S. Slesazeck, U. Schroeder, T. Mikolajick, L. Larcher, A. Padovani

引用次数: 34

Modelling of 1T-NOR flash operations for consumption optimization and reliability investigation 用于消耗优化和可靠性调查的1T-NOR闪存操作建模

2016 IEEE International Reliability Physics Symposium (IRPS) Pub Date : 2016-04-17 DOI: 10.1109/IRPS.2016.7574630

J. Coignus, G. Torrente, A. Vernhet, S. Renard, D. Roy, G. Reimbold

引用次数: 4

Positive bias temperature instability evaluation in fully recessed gate GaN MIS-FETs 全凹槽栅GaN misfet的正偏置温度不稳定性评估

2016 IEEE International Reliability Physics Symposium (IRPS) Pub Date : 2016-04-17 DOI: 10.1109/IRPS.2016.7574527

Tian-Li Wu, J. Franco, D. Marcon, B. de Jaeger, B. Bakeroot, X. Kang, S. Stoffels, M. Van Hove, G. Groeseneken, S. Decoutere

{"title":"Positive bias temperature instability evaluation in fully recessed gate GaN MIS-FETs","authors":"Tian-Li Wu, J. Franco, D. Marcon, B. de Jaeger, B. Bakeroot, X. Kang, S. Stoffels, M. Van Hove, G. Groeseneken, S. Decoutere","doi":"10.1109/IRPS.2016.7574527","DOIUrl":"https://doi.org/10.1109/IRPS.2016.7574527","url":null,"abstract":"In this paper, positive bias temperature instability (PBTI) in fully recessed gate GaN MIS-FETs is studied by using an eMSM (extended Measure-Stress-Measure) technique, which consists of a set of stress/recovery tests. By using this technique, VTH shift after a stress and the relaxation information can be collected in one experiment. First of all, a typical forward-reverse gate sweep and frequency-dependent conductance method are used to characterize VTH shift and interface state density (Dit) in fully recessed gate MIS-FETs with two different gate dielectrics (PEALD SiN and ALD Al2O3), showing that ALD Al2O3 has a smaller VTH shift compared with PEALD SiN although the latter has a smaller Dit. Then, an eMSM technique is used to understand the trapping/de-trapping phenomena under stress and relaxation period. The results show a power law dependency of VTH shift with respect to the stress time. Furthermore, the voltage dependency of VTH shift (7) can be extracted, showing that ALD Al2O3 has a higher 7 compared to PEALD SiN. The physical model is proposed to explain the mechanism for the different voltage dependency. On the other hand, the relaxation data is collected as well, indicating that Al2O3 has a faster relaxation even under a high voltage overdrive stress, which is consistent with physical model since accessibility of defects in Al2O3 are located at energies less favorable for channel carriers, compared to SiN.","PeriodicalId":172129,"journal":{"name":"2016 IEEE International Reliability Physics Symposium (IRPS)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124026048","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

Hot carrier stress: Aging modeling and analysis of defect location 热载流子应力:老化建模与缺陷定位分析

2016 IEEE International Reliability Physics Symposium (IRPS) Pub Date : 2016-04-17 DOI: 10.1109/IRPS.2016.7574546

G. Torrente, X. Federspiel, D. Rideau, F. Monsieur, C. Tavernier, J. Coignus, D. Roy, G. Ghibaudo

引用次数: 4

Highly-accelerated WLR learning cycles for development of a trench MOSFET: Method and case study 用于开发沟槽MOSFET的高加速WLR学习周期:方法和案例研究

2016 IEEE International Reliability Physics Symposium (IRPS) Pub Date : 2016-04-17 DOI: 10.1109/IRPS.2016.7574629

D. Moore, G. Hall, Masaru Suzuki, Peter Burke

引用次数: 0

SE performance of a Schmitt-trigger-based D-flip-flop design in a 16-nm bulk FinFET CMOS process 基于schmitt触发器的d触发器设计在16纳米体FinFET CMOS工艺中的SE性能

2016 IEEE International Reliability Physics Symposium (IRPS) Pub Date : 2016-04-17 DOI: 10.1109/IRPS.2016.7574517

H. Jiang, H. Zhang, D. Ball, L. Massengill, B. Bhuva, T. Assis, B. Narasimham

引用次数: 6

Adhesion requirements for photovoltaic modules of polymeric encapsulation 聚合物封装光伏组件的附着力要求

2016 IEEE International Reliability Physics Symposium (IRPS) Pub Date : 2016-04-17 DOI: 10.1109/IRPS.2016.7574636

Jiang Zhu, Gabriel Surier, Dan Wu, Daniel Montiel-Chicharro, T. Betts, R. Gottschalg

{"title":"Adhesion requirements for photovoltaic modules of polymeric encapsulation","authors":"Jiang Zhu, Gabriel Surier, Dan Wu, Daniel Montiel-Chicharro, T. Betts, R. Gottschalg","doi":"10.1109/IRPS.2016.7574636","DOIUrl":"https://doi.org/10.1109/IRPS.2016.7574636","url":null,"abstract":"Adhesion requirements for PV are often discussed but a detailed quantification based on scientific principles is outstanding. A test for the realistic assessment of requirements is presented. The difference between this test and the conventional peel test is that the test is conducted in-situ during ageing experiments in the climatic cabinet at realistic operating temperatures. Weights are attached to the backsheet of tested PV mini-modules to test stability of adhesion as devices being aged. This test is designed to identify the weakest interface of the multilayer encapsulation system and investigate the difference between field tests and failures (not) observed in certification testing. A series of samples was prepared under a wide range of lamination conditions. Different failure modes and ageing characteristics were observed. Some samples suffered quick failure of the adhesive bonds in the encapsulation system while others withstood forces of 20g/cm for 1000 hours. The test allows a clear discrimination between different samples and links closely to operational requirements.","PeriodicalId":172129,"journal":{"name":"2016 IEEE International Reliability Physics Symposium (IRPS)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122839370","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

On why dielectric breakdown strength reduces with dielectric thickness 介电击穿强度随介电厚度减小的原因分析

2016 IEEE International Reliability Physics Symposium (IRPS) Pub Date : 2016-04-17 DOI: 10.1109/IRPS.2016.7574512

J. McPherson

引用次数: 11

Device breakdown optimization of AhOs/GaN MISFETs AhOs/GaN misfet器件击穿优化

2016 IEEE International Reliability Physics Symposium (IRPS) Pub Date : 2016-04-17 DOI: 10.1109/IRPS.2016.7574589

X. Kang, D. Wellekens, M. Van Hove, B. de Jaeger, N. Ronchi, T.-L. Wu, S. You, B. Bakeroot, J. Hu, D. Marcon, S. Stoffels, S. Decoutere

{"title":"Device breakdown optimization of AhOs/GaN MISFETs","authors":"X. Kang, D. Wellekens, M. Van Hove, B. de Jaeger, N. Ronchi, T.-L. Wu, S. You, B. Bakeroot, J. Hu, D. Marcon, S. Stoffels, S. Decoutere","doi":"10.1109/IRPS.2016.7574589","DOIUrl":"https://doi.org/10.1109/IRPS.2016.7574589","url":null,"abstract":"In this paper we demonstrate a solution to achieve robust enhancement-mode Al2O3/GaN MISFETs with a high breakdown voltage and suggest a possible model for the device off-state breakdown. It is found that the device breakdown exhibits different gate voltage dependence for different surface treatments before the gate dielectric deposition. The device performance is greatly improved by using an in-situ surface plasma treatment. The improved device performance is explained by a reduction of traps at the Al2O3/GaN interface, which finally leads to a reduction in the amount of trapped positive charges and associated with that a reduction of the effective electric field across the gate dielectric when the device is in off-state. Several experimental results support this hypothesis: (1) The recoverable negative threshold voltage shift after reverse gate bias depends on the interface clean before gate dielectric deposition, (2) The reverse bias gate dielectric breakdown voltage is improved by this interface plasma treatment, although the forward bias gate dielectric breakdown voltage is identical.","PeriodicalId":172129,"journal":{"name":"2016 IEEE International Reliability Physics Symposium (IRPS)","volume":"59 23","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120888895","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4