H. Shim, Yoohwan Kim, J. Jeon, Y. Cho, Jongwoo Park, S. Pae, Haebum Lee
{"title":"Mismatch circuit aging modeling and simulations for robust product design and pre-/post-silicon verification","authors":"H. Shim, Yoohwan Kim, J. Jeon, Y. Cho, Jongwoo Park, S. Pae, Haebum Lee","doi":"10.1109/IRPS.2016.7574591","DOIUrl":"https://doi.org/10.1109/IRPS.2016.7574591","url":null,"abstract":"As technology scales down, PMOS NBTI-induced mismatch, in addition to the NBTI mean-shifts and time0-Vt variation, is critical for designing circuitry having matched pair transistors, such as OP amplifier. This paper covers mismatch aging models incorporated into design simulation tool for PMIC products and used the Monte-Carlo simulation to consider process and systematic variations for robust design. Circuit simulation for PMIC OP Amp and its output characteristics were investigated and then further validated through the post-silicon HTOL stress. The pre-silicon simulation further enables to optimize HTOL stress conditions.","PeriodicalId":172129,"journal":{"name":"2016 IEEE International Reliability Physics Symposium (IRPS)","volume":"151 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115447598","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
L. Heis, Andreas Lachmann, R. Schwab, G. Panagopoulos, Peter Baumgartner, Mamatha Yakkegondi Virupakshappaa, D. Schmitt-Landsiedel
{"title":"New methodology for on-chip RF reliability assessment","authors":"L. Heis, Andreas Lachmann, R. Schwab, G. Panagopoulos, Peter Baumgartner, Mamatha Yakkegondi Virupakshappaa, D. Schmitt-Landsiedel","doi":"10.1109/IRPS.2016.7574541","DOIUrl":"https://doi.org/10.1109/IRPS.2016.7574541","url":null,"abstract":"This work presents a systematic approach to investigate transistor reliability at high frequencies with on-chip stress circuits. The problem of state-of-the art on-chip stress circuits is that the actual stress signal at the device cannot be verified by measurements. However, due to the exponential voltage dependency of transistor reliability mechanisms it is important to know the exact voltage of the generated stress signals. Therefore our RF reliability assessment methodology uses two test structures, one to generate AC stress signals on-chip and one to monitor these signals with an on-chip oscilloscope. The methodology is applied to study the frequency dependency of PBTI, NBTI and hot carrier degradation in a 28 nm high-k technology.","PeriodicalId":172129,"journal":{"name":"2016 IEEE International Reliability Physics Symposium (IRPS)","volume":"221 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115984698","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Chasin, M. Scholz, W. Guo, J. Franco, G. Potoms, A. Jourdain, D. Linten, G. van der Plas, P. Absil, E. Beyne
{"title":"Impact of wafer thinning on front-end reliability for 3D integration","authors":"A. Chasin, M. Scholz, W. Guo, J. Franco, G. Potoms, A. Jourdain, D. Linten, G. van der Plas, P. Absil, E. Beyne","doi":"10.1109/IRPS.2016.7574562","DOIUrl":"https://doi.org/10.1109/IRPS.2016.7574562","url":null,"abstract":"The impact of wafer thinning down to 5 μm Si thickness is assessed in advanced planar and finFET CMOS technologies. Both Bias Temperature Instability (BTI) and Electrostatic Discharge (ESD) reliability are not impacted by the reduction of the substrate thickness.","PeriodicalId":172129,"journal":{"name":"2016 IEEE International Reliability Physics Symposium (IRPS)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114938835","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Machine learning-based proactive data retention error screening in 1Xnm TLC NAND flash","authors":"Y. Nakamura, T. Iwasaki, K. Takeuchi","doi":"10.1109/IRPS.2016.7574632","DOIUrl":"https://doi.org/10.1109/IRPS.2016.7574632","url":null,"abstract":"A screening method to proactively reduce data retention, as well as program disturb errors. Repeated program disturb (P.D.) measurement indicates that 25% of P.D. errors are concentrated in 3.5% of the memory cells, called PD-weak cells. PD-weak cells have 2.4× worse data retention (D.R.) than non-PD-weak cells, therefore D.R. errors are reduced by PD-weak cell screening. Proactive D.R. detection is a new capability, because conventional retention testing time is too long for chip testing. In 1Xnm TLC NAND flash, removal of PD-weak cells with <;2% overhead extends D.R. by 20%. The measurement method is described, and machine learning is applied to detect PD-weak cells. Detection rate vs. cost is also compared for 3 learning algorithms.","PeriodicalId":172129,"journal":{"name":"2016 IEEE International Reliability Physics Symposium (IRPS)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131034794","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Negative-bias temperature instability of GaN MOSFETs","authors":"A. Guo, J. D. del Alamo","doi":"10.1109/IRPS.2016.7574526","DOIUrl":"https://doi.org/10.1109/IRPS.2016.7574526","url":null,"abstract":"We present a detailed study of the threshold voltage (Vt) instability of GaN n-MOSFETs under negative gate stress. We have investigated Vt shift, subthreshold swing (S) degradation and transconductance (gm) degradation under negative gate voltage stress of different duration at different stress voltages and temperatures. We have found that as stress duration, voltage magnitude and temperature increase, Vt shift (ΔVT) progresses through three regimes. Under low-stress, ΔVT is negative and recoverable, which is a result of electron detrapping from pre-existing oxide traps. Under mid-stress, ΔVT is positive and also recoverable. This appears to be due to temporary electron trapping in the GaN channel under the edges of the gate. For high-stress, there is an additional non-recoverable negative ΔVT, which is consistent with interface state generation.","PeriodicalId":172129,"journal":{"name":"2016 IEEE International Reliability Physics Symposium (IRPS)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121688212","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Y. Illarionov, M. Waltl, M. Furchi, T. Mueller, T. Grasser
{"title":"Reliability of single-layer MoS2 field-effect transistors with SiO2 and hBN gate insulators","authors":"Y. Illarionov, M. Waltl, M. Furchi, T. Mueller, T. Grasser","doi":"10.1109/IRPS.2016.7574543","DOIUrl":"https://doi.org/10.1109/IRPS.2016.7574543","url":null,"abstract":"We study the hysteresis and bias-temperature instabilities in single-layer MoS2 FETs with SiO2 and hBN gate insulators and attempt to capture the correlation between these phenomena. In agreement with previous literature reports, our results show that the use of hBN as a gate insulator reduces the hysteresis. Furthermore, we show that the impact of the bias-temperature instabilities is weaker for MoS2/hBN transistors. However, at higher temperature the reliability of MoS2/hBN FETs is reduced due to thermally activated charge trapping.","PeriodicalId":172129,"journal":{"name":"2016 IEEE International Reliability Physics Symposium (IRPS)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123953556","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
T. Shen, B. Rajagopalan, M. Silvestre, E. Ramanathan, A. S. Mahalingam, Wenyi Zhang, K. Yeap, P. Justison
{"title":"Optimizing Cu barrier thickness for interconnects performance, reliability and yield","authors":"T. Shen, B. Rajagopalan, M. Silvestre, E. Ramanathan, A. S. Mahalingam, Wenyi Zhang, K. Yeap, P. Justison","doi":"10.1109/IRPS.2016.7574614","DOIUrl":"https://doi.org/10.1109/IRPS.2016.7574614","url":null,"abstract":"Cu barrier thickness optimization on our 90nm pitch Vx/Mx layers with porous ULK SiCOH (κ=2.55) was systematically investigated. Both via resistance and intrinsic EM performance favors thinner TaN and Ta films, however, the robustness of the plating requires thicker Ta to improve seed quality that withstand dissolution during plating. Overall, a thin TaN barrier with moderate thick Ta provides the optimum solution for performance, reliability and yield.","PeriodicalId":172129,"journal":{"name":"2016 IEEE International Reliability Physics Symposium (IRPS)","volume":"763 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116132401","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
C. Wu, Y. Li, J. Bommels, I. De Wolf, Z. Tokei, K. Croes
{"title":"New breakdown mechanism investigation: Barrier metal penetration induced soft breakdown in low-k dielectrics","authors":"C. Wu, Y. Li, J. Bommels, I. De Wolf, Z. Tokei, K. Croes","doi":"10.1109/IRPS.2016.7574511","DOIUrl":"https://doi.org/10.1109/IRPS.2016.7574511","url":null,"abstract":"A Soft Breakdown (SBD) phenomenon happening in porous low-k dielectrics during time dependent dielectric breakdown measurements was investigated. The early formation of local conductive paths was identified by monitoring leakage currents and capacitance data in the SBD phase. The nature of this conductive path was demonstrated to be related to intrinsic dielectric degradation. By comparing samples with different process conditions, we found that barrier metal penetration is an important root cause of SBD initiation. Our study of the voltage and temperature acceleration of the SBD phenomenon shows that these acceleration factors, m=22 and Ea=0.2eV, are at a reasonable level. However, further investigations on large size devices illustrate that the difference in barrier metal penetration depth between different samples could lead to a large decrease of Weibull slopes and degrade the overall reliability performance. Therefore, innovations of metal barrier deposition on porous low-k dielectrics to avoid barrier metal penetration are required for advanced technology nodes.","PeriodicalId":172129,"journal":{"name":"2016 IEEE International Reliability Physics Symposium (IRPS)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117166658","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Progressive breakdown in high-voltage GaN MIS-HEMTs","authors":"Shireen Warnock, J. D. del Alamo","doi":"10.1109/IRPS.2016.7574531","DOIUrl":"https://doi.org/10.1109/IRPS.2016.7574531","url":null,"abstract":"We have investigated the time-dependent dielectric breakdown (TDDB) characteristics of high-voltage AlGaN/GaN Metal-Insulator-Semiconductor High Electron Mobility Transistors (MIS-HEMTs). We focus in particular on the phenomenon known as progressive breakdown (PBD), marked by an onset of noise in the gate current IG during forward gate bias stress. We observe classic PBD behavior characterized by a rapid increase of IG noise during stress that takes place soon before hard breakdown (HBD). The onset of PBD also marks a change in the subthreshold characteristics of the transistor: the gate leakage increases above the measurement noise floor in a step-like fashion, with this additional leakage flowing out the source and/or drain terminals. After PBD, the subthreshold IG also shows a power law temperature dependence. The capacitance-voltage characteristics measured both before and after PBD confirm that device degradation does not occur at the AlGaN/GaN interface. All results are consistent with observations in silicon MOSFETs that support the percolation model of defects behind PBD and HBD. This gives hope that proper physical models suitable for lifetime estimation can be developed for TDDB in GaN MIS-HEMTs.","PeriodicalId":172129,"journal":{"name":"2016 IEEE International Reliability Physics Symposium (IRPS)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117225662","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Hai Jiang, S. Shin, Xiaoyan Liu, Xing Zhang, M. Alam
{"title":"Characterization of self-heating leads to universal scaling of HCI degradation of multi-fin SOI FinFETs","authors":"Hai Jiang, S. Shin, Xiaoyan Liu, Xing Zhang, M. Alam","doi":"10.1109/IRPS.2016.7574506","DOIUrl":"https://doi.org/10.1109/IRPS.2016.7574506","url":null,"abstract":"SOI FinFETs and other Gate-all-around (GAA) transistors topologies have excellent 3-D electrostatic control and therefore, have been suggested as potential technology options for sub-14 nm technology nodes. Unfortunately, the narrow gate geometry and reduced gate pitch suppress heat dissipation and increase thermal cross-talk, leading to severe self-heating of these transistors. Self-heating degrades performance and makes the classical reliability theories based on T<sub>L</sub>~T<sub>sub</sub> irrelevant. In this paper, first, we propose a physics-based thermal circuit compact model for multi-fin SOI FinFETs to characterize self-heating and validate the results by AC conductance method. Next, we analyze HCI degradation varying with the number of fin (N<sub>fin</sub>), chuck temperature (T<sub>sub</sub>) and AC frequency (f). The results show that HCI degradation dependent variables (N<sub>FIN</sub>, T<sub>sub</sub>, f) can be correlated to the lattice temperature (T<sub>L</sub> = g(N<sub>FIN</sub>, T<sub>sub</sub>, f)) and obey the universal degradation curve (ΔV<sub>th</sub>(T<sub>L</sub>) = f(S(T<sub>L</sub>) × t)). Si-O bond-dispersion model explains the universal curve; therefore, the model can be used for a long term reliability projection with arbitrary combination N<sub>fin</sub>, T<sub>sub</sub>, f, etc.","PeriodicalId":172129,"journal":{"name":"2016 IEEE International Reliability Physics Symposium (IRPS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133907557","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}