Mismatch circuit aging modeling and simulations for robust product design and pre-/post-silicon verification

Abstract

As technology scales down, PMOS NBTI-induced mismatch, in addition to the NBTI mean-shifts and time0-Vt variation, is critical for designing circuitry having matched pair transistors, such as OP amplifier. This paper covers mismatch aging models incorporated into design simulation tool for PMIC products and used the Monte-Carlo simulation to consider process and systematic variations for robust design. Circuit simulation for PMIC OP Amp and its output characteristics were investigated and then further validated through the post-silicon HTOL stress. The pre-silicon simulation further enables to optimize HTOL stress conditions.