Impact of wafer thinning on front-end reliability for 3D integration

2016 IEEE International Reliability Physics Symposium (IRPS) Pub Date : 2016-04-17 DOI:10.1109/IRPS.2016.7574562

A. Chasin, M. Scholz, W. Guo, J. Franco, G. Potoms, A. Jourdain, D. Linten, G. van der Plas, P. Absil, E. Beyne

引用次数: 6

Abstract

The impact of wafer thinning down to 5 μm Si thickness is assessed in advanced planar and finFET CMOS technologies. Both Bias Temperature Instability (BTI) and Electrostatic Discharge (ESD) reliability are not impacted by the reduction of the substrate thickness.

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晶圆减薄对3D集成前端可靠性的影响

在先进的平面和finFET CMOS技术中，评估了硅片减薄至5 μm Si厚度的影响。偏置温度不稳定性(BTI)和静电放电(ESD)可靠性不受衬底厚度减小的影响。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

2016 IEEE International Reliability Physics Symposium (IRPS)

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