New methodology for on-chip RF reliability assessment

Abstract

This work presents a systematic approach to investigate transistor reliability at high frequencies with on-chip stress circuits. The problem of state-of-the art on-chip stress circuits is that the actual stress signal at the device cannot be verified by measurements. However, due to the exponential voltage dependency of transistor reliability mechanisms it is important to know the exact voltage of the generated stress signals. Therefore our RF reliability assessment methodology uses two test structures, one to generate AC stress signals on-chip and one to monitor these signals with an on-chip oscilloscope. The methodology is applied to study the frequency dependency of PBTI, NBTI and hot carrier degradation in a 28 nm high-k technology.