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Impact of local stress in 3D stacking process on memory retention characteristics in thinned DRAM chip 3D堆叠过程中局部应力对薄化DRAM芯片记忆保持特性的影响
2016 IEEE International Reliability Physics Symposium (IRPS) Pub Date : 2016-04-17 DOI: 10.1109/IRPS.2016.7574561
S. Tanikawa, H. Kino, T. Fukushima, K. Lee, M. Koyanagi, T. Tanaka
{"title":"Impact of local stress in 3D stacking process on memory retention characteristics in thinned DRAM chip","authors":"S. Tanikawa, H. Kino, T. Fukushima, K. Lee, M. Koyanagi, T. Tanaka","doi":"10.1109/IRPS.2016.7574561","DOIUrl":"https://doi.org/10.1109/IRPS.2016.7574561","url":null,"abstract":"The effect of local stresses on memory retention characteristics has been characterized in detail. A retention time of memory cells in a DRAM chip with 200-μm thick was largely changed after under-fill shrinkage with Cu/Sn bumps. Meanwhile, after thinned down to 40-μm thick, the retention time of memory cell was not significantly changed in the whole area even with Cu/Sn bumps due to decreased stress. We showed that the local stress generated by under-fill shrinkage with the dummy Cu/Sn bumps gave larger effects on the memory retention characteristics than the stress generated by the Si thinning until 40-μm thick.","PeriodicalId":172129,"journal":{"name":"2016 IEEE International Reliability Physics Symposium (IRPS)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134399562","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Mission profile recorder: An aging monitor for hard events 任务剖面记录器:用于硬事件的老化监视器
2016 IEEE International Reliability Physics Symposium (IRPS) Pub Date : 2016-04-17 DOI: 10.1109/IRPS.2016.7574539
S. Mhira, V. Huard, A. Jain, F. Cacho, D. Meyer, S. Naudet, A. Bravaix, C. Parthasarathy
{"title":"Mission profile recorder: An aging monitor for hard events","authors":"S. Mhira, V. Huard, A. Jain, F. Cacho, D. Meyer, S. Naudet, A. Bravaix, C. Parthasarathy","doi":"10.1109/IRPS.2016.7574539","DOIUrl":"https://doi.org/10.1109/IRPS.2016.7574539","url":null,"abstract":"This work demonstrates the fundamental aspects of Mission Profile Recording as an alternative to intrusive, aging monitoring systems to cope with oxide breakdown and electromigration degradation mechanisms. A functional prototype is designed, implemented and fully tested on several wafers to achieve a full proof-of-concept. This study offers new perspectives towards product hardening and qualification with respect to an adaptive approach to real user-based workloads.","PeriodicalId":172129,"journal":{"name":"2016 IEEE International Reliability Physics Symposium (IRPS)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134411734","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Influence of metallization layout on aging detector lifetime under cyclic thermo-mechanical stress 循环热机械应力下金属化布局对老化探测器寿命的影响
2016 IEEE International Reliability Physics Symposium (IRPS) Pub Date : 2016-04-17 DOI: 10.1109/IRPS.2016.7574551
G. Pham, M. Ritter, M. Pfost
{"title":"Influence of metallization layout on aging detector lifetime under cyclic thermo-mechanical stress","authors":"G. Pham, M. Ritter, M. Pfost","doi":"10.1109/IRPS.2016.7574551","DOIUrl":"https://doi.org/10.1109/IRPS.2016.7574551","url":null,"abstract":"The influence of the layout on early warning detectors in BCD technologies for metallization failure under cyclic thermo-mechanical stress was investigated. Different LDMOS transistors, with narrow or wide metal fingers and with or without embedded detectors, were used. The test structures were repeatedly stressed by pronounced self-heating until failure (a short circuit) was detected. The results show that the layout of the on-chip metallization has a large impact on the lifetime. A significant influence of the detectors on the lifetime was also observed, in our case causing a reduction of more than a factor of two, but only for the test structure with narrow metal fingers. The experimental results are explained by an efficient numerical thermo-mechanical simulation approach, giving detailed insights into the strain distribution in the metal system. These results are important for aging detector design and, morever, for LDMOS on-chip metal layout in general.","PeriodicalId":172129,"journal":{"name":"2016 IEEE International Reliability Physics Symposium (IRPS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130683811","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Data archiving in 1x-nm NAND flash memories: Enabling long-term storage using rank modulation and scrubbing 1x-nm NAND闪存中的数据归档:使用等级调制和擦除实现长期存储
2016 IEEE International Reliability Physics Symposium (IRPS) Pub Date : 2016-04-17 DOI: 10.1109/IRPS.2016.7574572
Yue Li, Eyal En Gad, Anxiao Jiang, Jehoshua Bruck
{"title":"Data archiving in 1x-nm NAND flash memories: Enabling long-term storage using rank modulation and scrubbing","authors":"Yue Li, Eyal En Gad, Anxiao Jiang, Jehoshua Bruck","doi":"10.1109/IRPS.2016.7574572","DOIUrl":"https://doi.org/10.1109/IRPS.2016.7574572","url":null,"abstract":"The challenge of using inexpensive and high-density NAND flash for archival storage was posed recently for reducing data center costs. However, such flash memory is becoming more susceptible to noise, and its reliability issues has become the major concern for its adoption by long-term storage systems. This paper studies the system-level reliability of archival storage that uses 1x-nm NAND flash memory. We analyze retention error behavior, and show that 1x-nm MLC and TLC flash do not immediately qualify for long-term storage. We then implement the rank modulation (RM) scheme and memory scrubbing (MS) for retention period (RP) enhancement. The RM scheme provides a new data representation using the relative order of cell voltages, which provides higher reliability against uniform asymmetric threshold voltage shift due to charge leakage. Results show that the new representation reduces raw bit error rate (RBER) by 45% on average, and using RM and MS together provides up to 196, 171, 146 and 121 years of RPs for blocks with 0, 25, 50 and 75 program/erase cycles, respectively.","PeriodicalId":172129,"journal":{"name":"2016 IEEE International Reliability Physics Symposium (IRPS)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122290005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Improvement of DSSC performance by voltage stress application 施加电压应力对DSSC性能的改善
2016 IEEE International Reliability Physics Symposium (IRPS) Pub Date : 2016-04-17 DOI: 10.1109/IRPS.2016.7574635
A. Scuto, S. Lombardo, G. Di Marco, G. Calogero, I. Citro, F. Principato, Clara Chiappara
{"title":"Improvement of DSSC performance by voltage stress application","authors":"A. Scuto, S. Lombardo, G. Di Marco, G. Calogero, I. Citro, F. Principato, Clara Chiappara","doi":"10.1109/IRPS.2016.7574635","DOIUrl":"https://doi.org/10.1109/IRPS.2016.7574635","url":null,"abstract":"Dye-sensitized solar cells (DSSCs) are promising third generation photovoltaic devices given their potential low cost and high efficiency. Some factors still affect DSSCs performance, such structure of electrodes, electrolyte compositions, nature of the sensitizers, power conversion efficiency, long-term stability, etc. In this work we discuss the effect of electrical stresses, which allow to improve DSSC performance. We have investigated the outcomes of forward and reverse DC bias stress as a function of time, voltage, and illumination level in the DSSCs sensitized with the N719, Ruthenium complex based dye. We demonstrate that all the major solar cell parameters, i.e., open circuit voltage (VOC), short circuit current (ISC), series resistance (ROC), fill factor (FF), and power conversion efficiency are strongly influenced by the stress conditions and a clear reversibility of the parameters on the stress type is shown. In this context we examined the possible effects that emerge from the electrolyte composition.","PeriodicalId":172129,"journal":{"name":"2016 IEEE International Reliability Physics Symposium (IRPS)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114377359","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A compact model for RRAM including random telegraph noise 包含随机电报噪声的RRAM的紧凑模型
2016 IEEE International Reliability Physics Symposium (IRPS) Pub Date : 2016-04-17 DOI: 10.1109/IRPS.2016.7574621
Bochen Guan, Jing Li
{"title":"A compact model for RRAM including random telegraph noise","authors":"Bochen Guan, Jing Li","doi":"10.1109/IRPS.2016.7574621","DOIUrl":"https://doi.org/10.1109/IRPS.2016.7574621","url":null,"abstract":"In this paper, we develop a RRAM compact model accounting for random telegraph noise (RTN) effect. In particular, we develop a Monte Carlo method to effectively capture the behaviors of the traps in the tunneling gap, which can be used to predict the current fluctuation caused by RTN. The model is validated with experimental data under various operating conditions. The model can be applied to study RRAM circuit reliability for efficient design space explorations.","PeriodicalId":172129,"journal":{"name":"2016 IEEE International Reliability Physics Symposium (IRPS)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127621536","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Comparative experimental analysis of time-dependent variability using a transistor test array 使用晶体管测试阵列的时变特性对比实验分析
2016 IEEE International Reliability Physics Symposium (IRPS) Pub Date : 2016-04-17 DOI: 10.1109/IRPS.2016.7574652
Marko Simicic, A. Subirats, P. Weckx, B. Kaczer, J. Franco, P. Roussel, D. Linten, A. Thean, G. Groeseneken, G. Gielen
{"title":"Comparative experimental analysis of time-dependent variability using a transistor test array","authors":"Marko Simicic, A. Subirats, P. Weckx, B. Kaczer, J. Franco, P. Roussel, D. Linten, A. Thean, G. Groeseneken, G. Gielen","doi":"10.1109/IRPS.2016.7574652","DOIUrl":"https://doi.org/10.1109/IRPS.2016.7574652","url":null,"abstract":"As the minimum transistor length reaches the deca-nanometer scale, both time-zero and time-dependent variability, the latter including Random Telegraph Noise (RTN) and Bias Temperature Instability (BTI), become a great concern for IC design. Accurate statistical models describing these two variability sources are therefore necessary in order to design reliable circuits and systems. This paper gives insights in the geometric scaling of these variabilities and analyzes time-dependent variability through three different measurement techniques: 2-point Measure-Stress-Measure, Time-Dependent Defect Spectroscopy, and fine-step Id-Vg. Advantages and downsides of each technique are discussed and compared.","PeriodicalId":172129,"journal":{"name":"2016 IEEE International Reliability Physics Symposium (IRPS)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128000901","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Reliability-performance tradeoffs between 2.5D and 3D-stacked DRAM processors 2.5D和3d堆叠DRAM处理器之间的可靠性性能权衡
2016 IEEE International Reliability Physics Symposium (IRPS) Pub Date : 2016-04-17 DOI: 10.1109/IRPS.2016.7574618
S. M. Hassan, William J. Song, S. Mukhopadhyay, S. Yalamanchili
{"title":"Reliability-performance tradeoffs between 2.5D and 3D-stacked DRAM processors","authors":"S. M. Hassan, William J. Song, S. Mukhopadhyay, S. Yalamanchili","doi":"10.1109/IRPS.2016.7574618","DOIUrl":"https://doi.org/10.1109/IRPS.2016.7574618","url":null,"abstract":"Three-dimensional DRAM stacking has emerged as a vehicle for scaling system densities and performance improvement. The two design choices for interfacing to processors are - i) a separate core die connected to the DRAM stack via a silicon interposer (2.5D), and ii) DRAM die stacked on top of the core die (3D). These alternatives have different performance, power, and reliability behaviors. Specifically, 3D designs realize higher performance but operate at higher temperatures and thus exhibit lower lifetime. On the other hand, 2.5D designs provide lower bandwidth between the core die and the DRAM stack, but exhibit significantly longer lifetime due to less thermally-induced degradation. This paper explores this tradeoff between reliability and performance of 3D and 2.5D stacked memory systems. Our results indicate that, in general, lower voltage and frequency operations with 3D stacked systems may achieve balanced reliability-performance tradeoff.","PeriodicalId":172129,"journal":{"name":"2016 IEEE International Reliability Physics Symposium (IRPS)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131534538","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Process optimizations for NBTI/PBTI for future replacement metal gate technologies 优化NBTI/PBTI的工艺，为未来替代金属栅极技术
2016 IEEE International Reliability Physics Symposium (IRPS) Pub Date : 2016-04-17 DOI: 10.1109/IRPS.2016.7574532
B. Linder, A. Dasgupta, T. Ando, E. Cartier, U. Kwon, R. Southwick, M. Wang, S. Krishnan, M. Hopstaken, M. Bajaj, R. Pandey, W. Chang, T. Yamashita, O. Gluschenkov, V. Narayanan, J. Stathis, S. Ray, J. Liu
{"title":"Process optimizations for NBTI/PBTI for future replacement metal gate technologies","authors":"B. Linder, A. Dasgupta, T. Ando, E. Cartier, U. Kwon, R. Southwick, M. Wang, S. Krishnan, M. Hopstaken, M. Bajaj, R. Pandey, W. Chang, T. Yamashita, O. Gluschenkov, V. Narayanan, J. Stathis, S. Ray, J. Liu","doi":"10.1109/IRPS.2016.7574532","DOIUrl":"https://doi.org/10.1109/IRPS.2016.7574532","url":null,"abstract":"Bias Temperature Instability (BTI) is a tremendous reliability concern for deeply scaled CMOS technologies, and is the limiting mechanism for further inversion layer thickness (Tinv) scaling for future nodes [1]. Replacement Metal Gate technologies are of particular concern, since the gate stack is not exposed to the high temperature source/drain anneals. We have identified four strategies for reducing BTI in Replacement metal gate technologies: Rapid Thermal Anneal (RTA) optimization, optimization of the HfO2 layer thickness, introducing a gate dielectric dopant for NBTI reduction, and effective Work Function tuning. Judiciously combining these four techniques enable further Tinv scaling for 10 nm and below.","PeriodicalId":172129,"journal":{"name":"2016 IEEE International Reliability Physics Symposium (IRPS)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123853788","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Power-supply impact on the reliability of mid-1X TLC NAND flash memories 电源对mid-1X TLC NAND闪存可靠性的影响
2016 IEEE International Reliability Physics Symposium (IRPS) Pub Date : 2016-04-17 DOI: 10.1109/IRPS.2016.7574509
C. Zambelli, Pietro King, P. Olivo, L. Crippa, R. Micheloni
{"title":"Power-supply impact on the reliability of mid-1X TLC NAND flash memories","authors":"C. Zambelli, Pietro King, P. Olivo, L. Crippa, R. Micheloni","doi":"10.1109/IRPS.2016.7574509","DOIUrl":"https://doi.org/10.1109/IRPS.2016.7574509","url":null,"abstract":"NAND Flash memories are complex systems that include many heterogeneous blocks that must work together to ensure a high reliability of the information storage. Many efforts in the reliability community are devoted to investigate the reliability-loss of this storage medium from a cell device physics point of view, whereas little importance is given to the other blocks that constitute such a system. In this work we present a reliability threat related to NAND Flash memories that is present on the high voltage circuitry of the memory: the dependence on the power supply. Through the experimental characterization of TLC mid-1X samples and thanks to the SPICE simulations of the high voltage blocks we have investigated the possible sources of this new reliability issue.","PeriodicalId":172129,"journal":{"name":"2016 IEEE International Reliability Physics Symposium (IRPS)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124686998","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
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