{"title":"Failure mechanism of high-voltage isolated lateral diffused NMOS under high-current events","authors":"Cheng-Hsu Wu, C. Lien, Jian-Hsing Lee","doi":"10.1109/IRPS.2016.7574603","DOIUrl":"https://doi.org/10.1109/IRPS.2016.7574603","url":null,"abstract":"In this study, the mechanism of the effect of a high-voltage (HV) NWell guardring (NW-GR) on the electrostatic discharge (ESD) robustness of the HV isolated lateral diffused NMOS (HV ISO-LDNMOS) is investigated. The device fails on low-voltage ESD zapping events when the HVNW-GR is connected to the drain, whereas the device passes these events once it is floated.","PeriodicalId":172129,"journal":{"name":"2016 IEEE International Reliability Physics Symposium (IRPS)","volume":"170 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121183080","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
G. Schindler, K. Bach, P. Nelle, M. Deckers, A. Knapp, K. Ermisch, C. Feuerbaum, W. Emden
{"title":"Impact of alpha-radiation on power MOSFETs","authors":"G. Schindler, K. Bach, P. Nelle, M. Deckers, A. Knapp, K. Ermisch, C. Feuerbaum, W. Emden","doi":"10.1109/IRPS.2016.7574553","DOIUrl":"https://doi.org/10.1109/IRPS.2016.7574553","url":null,"abstract":"In this paper it is shown how the impact of alpha particles in the gate oxide of a power MOSFET leads to a local reduction of the threshold voltage Vth. Evidence is presented that radioactive impurities in the solder material of the clip attach indeed are the root cause for such effects observed in long term measurements with electrical gate bias. Data show that alpha impacts have no negative influence on reliability and application performance of power MOSFETs.","PeriodicalId":172129,"journal":{"name":"2016 IEEE International Reliability Physics Symposium (IRPS)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116358116","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Stanley A. Ikpe, J. Lauenstein, G. Carr, D. Hunter, L. Ludwig, William A. Wood, C. Iannello, L. Del Castillo, Fred D. Fitzpatrick, M. Mojarradi, Yuan Chen
{"title":"Long-term reliability of a hard-switched boost power processing unit utilizing SiC power MOSFETs","authors":"Stanley A. Ikpe, J. Lauenstein, G. Carr, D. Hunter, L. Ludwig, William A. Wood, C. Iannello, L. Del Castillo, Fred D. Fitzpatrick, M. Mojarradi, Yuan Chen","doi":"10.1109/IRPS.2016.7574610","DOIUrl":"https://doi.org/10.1109/IRPS.2016.7574610","url":null,"abstract":"Silicon carbide (SiC) power devices have demonstrated many performance advantages over their silicon (Si) counterparts. As the inherent material limitations of Si devices are being swiftly realized, wide-bandgap (WBG) materials such as SiC have become increasingly attractive for high power applications. In particular, SiC power metal oxide semiconductor field effect transistors' (MOSFETs) high breakdown field tolerance, superior thermal conductivity and low-resistivity drift regions make these devices an excellent candidate for power dense, low loss, high frequency switching applications in extreme environment conditions. In this paper, a novel power processing unit (PPU) architecture is proposed utilizing commercially available 4H-SiC power MOSFETs from CREE Inc. A multiphase straight boost converter topology is implemented to supply up to 10 kW full-scale. High Temperature Gate Bias (HTGB) and High Temperature Reverse Bias (HTRB) characterization is performed to evaluate the long-term reliability of both the gate oxide and the body diode of the SiC components. Finally, susceptibility of the CREE SiC MOSFETs to damaging effects from heavy-ion radiation representative of the on-orbit galactic cosmic ray environment are explored. The results provide the baseline performance metrics of operation as well as demonstrate the feasibility of a hard-switched PPU in harsh environments.","PeriodicalId":172129,"journal":{"name":"2016 IEEE International Reliability Physics Symposium (IRPS)","volume":"272 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122535691","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Trippe, R. Reed, B. Sierawski, R. Weller, R. Austin, L. Massengill, B. Bhuva, K. Warren, B. Narasimham
{"title":"Predicting the vulnerability of memories to muon-induced SEUs with low-energy proton tests informed by Monte Carlo simulations","authors":"J. Trippe, R. Reed, B. Sierawski, R. Weller, R. Austin, L. Massengill, B. Bhuva, K. Warren, B. Narasimham","doi":"10.1109/IRPS.2016.7574642","DOIUrl":"https://doi.org/10.1109/IRPS.2016.7574642","url":null,"abstract":"A method for predicting device vulnerability to muon induced single event upsets (SEUs) using proton tests and Monte Carlo simulations was developed and validated using a 28 nm commercial static random access memory (SRAM). This method replaces testing with muon beams while still incorporating the device's response to stopping charged particles. Monte Carlo simulations are used to relate energy deposition by stopping protons to that of muons. This mapping can be employed to determine the proton test energies required to simulate exposure to a muon environment. This method is superior to simulations since the device's empirical response to proton exposure is used to determine upper and lower particle energy bounds for muon susceptibility. This window of vulnerability can then be used to predict a conservative estimate of the soft error rate for muon exposures.","PeriodicalId":172129,"journal":{"name":"2016 IEEE International Reliability Physics Symposium (IRPS)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122960266","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Chasin, J. Franco, R. Ritzenthaler, G. Hellings, M. Cho, Y. Sasaki, A. Subirats, P. Roussel, B. Kaczer, D. Linten, N. Horiguchi, G. Groeseneken, A. Thean
{"title":"Hot-carrier analysis on nMOS Si FinFETs with solid source doped junction","authors":"A. Chasin, J. Franco, R. Ritzenthaler, G. Hellings, M. Cho, Y. Sasaki, A. Subirats, P. Roussel, B. Kaczer, D. Linten, N. Horiguchi, G. Groeseneken, A. Thean","doi":"10.1109/IRPS.2016.7574535","DOIUrl":"https://doi.org/10.1109/IRPS.2016.7574535","url":null,"abstract":"We report extensive experimental results of the Channel Hot Carrier (CHC) and Positive Bias Temperature Instability (PBTI) reliability of nMOS Si bulk-FinFETs with extension doping by PEALD Phosphorus doped Silicate Glass (PSG). Device performance improvements with PSG doping are achieved without substantial device reliability degradation even for short channel FinFETs. PSG results in better conformality and less damage in the junctions and lower Gate Induced Drain Leakage (GIDL) current than standard Phosphorous Ion Implantation process (P I/I).","PeriodicalId":172129,"journal":{"name":"2016 IEEE International Reliability Physics Symposium (IRPS)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115741004","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Data-retention time prediction of long-term archive SSD with flexible-nLC NAND flash","authors":"Tomonori Takahashi, Senju Yamazaki, K. Takeuchi","doi":"10.1109/IRPS.2016.7574571","DOIUrl":"https://doi.org/10.1109/IRPS.2016.7574571","url":null,"abstract":"This paper proposes a new method to predict the data-retention time of long-term archive SSD with flexible-nLC NAND flash. This paper first reports that the conventional prediction overestimates the data lifetime based on the long-term data retention measurement. Then, a more precise prediction is proposed. By using this proposal, the most reliable and lowest cost memory architecture is determined. As a result, over 100-year data-retention is achieved, which is 25-times longer than the conventional TLC NAND flash memory.","PeriodicalId":172129,"journal":{"name":"2016 IEEE International Reliability Physics Symposium (IRPS)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126123517","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
V. Vasudevan, Tanner Schulz, M. Pei, F. Toth, A. Lucero, Bite Zhou, Sibasish Mukherjee
{"title":"The state of Pb-free solder — A joint reliability overview","authors":"V. Vasudevan, Tanner Schulz, M. Pei, F. Toth, A. Lucero, Bite Zhou, Sibasish Mukherjee","doi":"10.1109/IRPS.2016.7574566","DOIUrl":"https://doi.org/10.1109/IRPS.2016.7574566","url":null,"abstract":"Over the past decade the electronics components industry successfully transitioned from the use of leaded solder to lead-free (Pb-free) solders in response to growing environmental health concerns related to heavy metals and other substances. Pbfree components in general are in compliance to meet the European restriction of hazardous substances (RoHS) directives. During the transition period to Pb-free surface mount, numerous issues were raised about the selected alloys, the board assembly process and reliability. Early Pb-free reliability concerns were due to incomplete analytical understanding of the Tin-Silver-Copper solder creep-fatigue behavior, difficulty in computing the magnitude of ball grid array (BGA) relative displacements or strains and lack of product field history. Since then the failure mechanisms were characterized and many models are in common use for reliability estimation and design. This manuscript revisits the initial concerns, reliability model use evolution and summarizes the current understanding that has resulted in a decade of reliable field operation for the Pb-free SAC solders selected.","PeriodicalId":172129,"journal":{"name":"2016 IEEE International Reliability Physics Symposium (IRPS)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127023328","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
R. Boschke, Shih-Hung Chen, G. Hellings, M. Scholz, P. De Heyn, P. Verheyen, J. Van Campenhout, D. Linten, A. Thean, G. Groeseneken
{"title":"Bidirectional NPN ESD protection in silicon photonics technology","authors":"R. Boschke, Shih-Hung Chen, G. Hellings, M. Scholz, P. De Heyn, P. Verheyen, J. Van Campenhout, D. Linten, A. Thean, G. Groeseneken","doi":"10.1109/IRPS.2016.7574520","DOIUrl":"https://doi.org/10.1109/IRPS.2016.7574520","url":null,"abstract":"Silicon photonics interposers enable low power, high bandwidth signal transfer between CMOS chips. Optical wave guides transfer the optical signal that carries the information. Optical modulator and detectors realize the optical to electrical signal transfer and vice versa. These components could be facing ESD stress during assembly. This work presents an in-depth study the self-protecting capabilities of these components and provides an ESD protection solution to increase the ESD robustness.","PeriodicalId":172129,"journal":{"name":"2016 IEEE International Reliability Physics Symposium (IRPS)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125455923","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Alteration of oxide-trap switching activity at operating condition by voltage-accelerated stressing","authors":"Z. Tung, D. Ang","doi":"10.1109/IRPS.2016.7574643","DOIUrl":"https://doi.org/10.1109/IRPS.2016.7574643","url":null,"abstract":"It is found that voltage-accelerated stressing can change the switching activity of a time-zero oxide defect measured under operating condition. The defect can be rendered either less active or more active by the applied stress, implying a possible modification of its atomic structure. With the impact of oxide trapping on MOSFET channel conduction becoming increasingly important as device dimension decreases, the observed stress-induced alteration of trap-switching behavior under operating condition should be a consideration in the reliability assessment of small-area devices.","PeriodicalId":172129,"journal":{"name":"2016 IEEE International Reliability Physics Symposium (IRPS)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122362667","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Mukhopadhyay, J. Franco, A. Chasin, P. Roussel, B. Kaczer, G. Groeseneken, N. Horiguchi, D. Linten, A. Thean
{"title":"Fundamental study of the apparent voltage-dependence of NBTI kinetics by constant electric field stress in Si and SiGe devices","authors":"S. Mukhopadhyay, J. Franco, A. Chasin, P. Roussel, B. Kaczer, G. Groeseneken, N. Horiguchi, D. Linten, A. Thean","doi":"10.1109/IRPS.2016.7574545","DOIUrl":"https://doi.org/10.1109/IRPS.2016.7574545","url":null,"abstract":"SiGe and Ge pMOSFETs, with channel passivation by Si cap and standard SiO2/HfO2 gate stack, show a very strong oxide electric field dependence of NBTI, beneficial for low voltage operation. However, standard NBTI extrapolation based on voltage accelerated stress tests is complicated for these devices due to an apparent correlation of time-dependence exponent (n) to the applied gate stress overdrive voltage (VOV). This behavior is found to be unrelated to the measurement delay, but induced by a gradual reduction of the stress oxide electric field during the NBTI stress due to the buildup of threshold voltage shift. A unique analog circuit based test setup is proposed to perform a quasi-constant oxide field BTI stress. This method eliminates the field reduction effect during NBTI stress and therefore decouples the time exponent from the applied stress VOV. This allows to calculate the time-to-failure for SiGe and Ge channel devices unambiguously, confirming the superior NBTI reliability of these pMOS technologies as compared to standard Si devices. Possible limitations of the proposed measurement method are also discussed.","PeriodicalId":172129,"journal":{"name":"2016 IEEE International Reliability Physics Symposium (IRPS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130475724","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}