{"title":"Negative-bias temperature instability of GaN MOSFETs","authors":"A. Guo, J. D. del Alamo","doi":"10.1109/IRPS.2016.7574526","DOIUrl":null,"url":null,"abstract":"We present a detailed study of the threshold voltage (Vt) instability of GaN n-MOSFETs under negative gate stress. We have investigated Vt shift, subthreshold swing (S) degradation and transconductance (gm) degradation under negative gate voltage stress of different duration at different stress voltages and temperatures. We have found that as stress duration, voltage magnitude and temperature increase, Vt shift (ΔVT) progresses through three regimes. Under low-stress, ΔVT is negative and recoverable, which is a result of electron detrapping from pre-existing oxide traps. Under mid-stress, ΔVT is positive and also recoverable. This appears to be due to temporary electron trapping in the GaN channel under the edges of the gate. For high-stress, there is an additional non-recoverable negative ΔVT, which is consistent with interface state generation.","PeriodicalId":172129,"journal":{"name":"2016 IEEE International Reliability Physics Symposium (IRPS)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"36","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE International Reliability Physics Symposium (IRPS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IRPS.2016.7574526","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 36
Abstract
We present a detailed study of the threshold voltage (Vt) instability of GaN n-MOSFETs under negative gate stress. We have investigated Vt shift, subthreshold swing (S) degradation and transconductance (gm) degradation under negative gate voltage stress of different duration at different stress voltages and temperatures. We have found that as stress duration, voltage magnitude and temperature increase, Vt shift (ΔVT) progresses through three regimes. Under low-stress, ΔVT is negative and recoverable, which is a result of electron detrapping from pre-existing oxide traps. Under mid-stress, ΔVT is positive and also recoverable. This appears to be due to temporary electron trapping in the GaN channel under the edges of the gate. For high-stress, there is an additional non-recoverable negative ΔVT, which is consistent with interface state generation.