Modelling of 1T-NOR flash operations for consumption optimization and reliability investigation

Abstract

Performance improvement of 1T-NOR Flash technology is demonstrated, thanks to the optimization of memory cell electrical operations. An electrical model is proposed, providing optimized program and erase electrical pulse patterns as a function of application-related constraints. Model output covers a wide operating range of single Flash cell, and allows to finely tune the consumption / charge pump scalability compromise. In the meanwhile, novel experimental capabilities allow the simulated electrical patterns to be applied along endurance characterization, and provide an extended description of Flash program dynamics along device aging. Optimized cycling conditions are shown to reduce power consumption with the cost of reduced program speed, but without any detrimental impact on device reliability.