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2016 IEEE International Reliability Physics Symposium (IRPS)最新文献

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Exploiting low power circuit topologies for soft error mitigation 利用低功耗电路拓扑实现软错误缓解
2016 IEEE International Reliability Physics Symposium (IRPS) Pub Date : 2016-09-26 DOI: 10.1109/IRPS.2016.7574640
N. Mahatme, I. Chatterjee, S. Jagannathan, N. Gaspard, T. Assis, S. Wen, R. Wong, B. Bhuva
{"title":"Exploiting low power circuit topologies for soft error mitigation","authors":"N. Mahatme, I. Chatterjee, S. Jagannathan, N. Gaspard, T. Assis, S. Wen, R. Wong, B. Bhuva","doi":"10.1109/IRPS.2016.7574640","DOIUrl":"https://doi.org/10.1109/IRPS.2016.7574640","url":null,"abstract":"Alpha particle experimental results for arithmetic circuits implemented using transmission gate logic are shown to have 35% lower soft error rate as well as 30% lower power consumption compared to standard CMOS circuits. Analytical models confirm the experimental trends and help optimize and predict the power-SER trade-off.","PeriodicalId":172129,"journal":{"name":"2016 IEEE International Reliability Physics Symposium (IRPS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129058145","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
On-chip protection in precision integrated circuits operating at high voltage and high temperature 在高电压和高温下工作的精密集成电路的片上保护
2016 IEEE International Reliability Physics Symposium (IRPS) Pub Date : 2016-09-26 DOI: 10.1109/IRPS.2016.7574605
James Zhao, J. Salcedo, J. Hajjar
{"title":"On-chip protection in precision integrated circuits operating at high voltage and high temperature","authors":"James Zhao, J. Salcedo, J. Hajjar","doi":"10.1109/IRPS.2016.7574605","DOIUrl":"https://doi.org/10.1109/IRPS.2016.7574605","url":null,"abstract":"A new high voltage swing bipolar ESD (electrostatic discharge) protection device for enabling low leakage precision mixed-signal interface circuits (ICs) operating at high voltage (~ 40 V to 60 V) and high temperature (~125°C to 200°C) is presented. Under these operating conditions, parasitic structures in junction-isolated high voltage process technologies induce unexpected shift in the leakage current over time, leading to malfunction in the precision high voltage input/output interface circuit. A proposed device design addresses the low leakage targets at the mentioned operating conditions, while achieving the required ESD robustness of the high voltage interface for industrial applications.","PeriodicalId":172129,"journal":{"name":"2016 IEEE International Reliability Physics Symposium (IRPS)","volume":"21 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129455838","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Improving the long pulse width failure current of NPN in BiCMOS technology 提高BiCMOS技术中NPN的长脉宽失效电流
2016 IEEE International Reliability Physics Symposium (IRPS) Pub Date : 2016-09-22 DOI: 10.1109/IRPS.2016.7574606
Yang Xiu, A. Appaswamy, Zaichen Chen, A. Salman, M. Dissegna, G. Boselli, E. Rosenbaum
{"title":"Improving the long pulse width failure current of NPN in BiCMOS technology","authors":"Yang Xiu, A. Appaswamy, Zaichen Chen, A. Salman, M. Dissegna, G. Boselli, E. Rosenbaum","doi":"10.1109/IRPS.2016.7574606","DOIUrl":"https://doi.org/10.1109/IRPS.2016.7574606","url":null,"abstract":"The pulse width dependency of the failure current for NPN structures in a 0.18-μm BiCMOS technology is studied using measurements and TCAD simulation. The desired “Wunsch-Bell” behavior is not observed due to formation of current filaments in this device; however, the failure current for long pulse widths can be increased by layout changes.","PeriodicalId":172129,"journal":{"name":"2016 IEEE International Reliability Physics Symposium (IRPS)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134499661","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Experimental study of supply voltage stability during ESD ESD过程中电源电压稳定性的实验研究
2016 IEEE International Reliability Physics Symposium (IRPS) Pub Date : 2016-09-22 DOI: 10.1109/IRPS.2016.7574560
Yang Xiu, R. Mertens, N. Thomson, E. Rosenbaum
{"title":"Experimental study of supply voltage stability during ESD","authors":"Yang Xiu, R. Mertens, N. Thomson, E. Rosenbaum","doi":"10.1109/IRPS.2016.7574560","DOIUrl":"https://doi.org/10.1109/IRPS.2016.7574560","url":null,"abstract":"On-chip power supply integrity may be compromised during a power-on ESD event, e.g. system-level ESD. Experimental data are provided to show that the supply integrity is a function of the rail clamp gain, its speed of response to ESD, and the amount of on-chip supply decoupling capacitance. It is also demonstrated that just a few nH of package inductance can cause the on-chip supply to briefly collapse, regardless of the rail clamp response speed.","PeriodicalId":172129,"journal":{"name":"2016 IEEE International Reliability Physics Symposium (IRPS)","volume":"201 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115475739","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
ESD self-protection design on 2.4-GHz T/R switch for RF application in CMOS process 基于CMOS工艺的2.4 ghz射频收发开关ESD自保护设计
2016 IEEE International Reliability Physics Symposium (IRPS) Pub Date : 2016-09-22 DOI: 10.1109/IRPS.2016.7574602
Chun-Yu Lin, Rui-Hong Liu, M. Ker
{"title":"ESD self-protection design on 2.4-GHz T/R switch for RF application in CMOS process","authors":"Chun-Yu Lin, Rui-Hong Liu, M. Ker","doi":"10.1109/IRPS.2016.7574602","DOIUrl":"https://doi.org/10.1109/IRPS.2016.7574602","url":null,"abstract":"An RF transceiver front-end for 2.4GHz applications realized by a fully integrated T/R switch with ESD self-protection capability is presented in this work. Experimental results show that the proposed design without using any additional ESD protection device can provide enough ESD self-protection capability with good RF performances.","PeriodicalId":172129,"journal":{"name":"2016 IEEE International Reliability Physics Symposium (IRPS)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123660869","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
On the variability of threshold voltage window in gate-injection versatile memories with Sub-60mV/dec subthreshold swing and 1012-cycling endurance 亚阈值摆幅低于60mv /dec的门注入通用存储器中阈值电压窗的可变性
2016 IEEE International Reliability Physics Symposium (IRPS) Pub Date : 2016-09-22 DOI: 10.1109/IRPS.2016.7574623
Y. Chiu, Chun-Yen Chang, S. Yen, C. Fan, H. Hsu, Chun‐Hu Cheng, Po‐Chun Chen, Po-Wei Chen, G. Liou, Min-Hung Lee, Chien Liu, Wu-Ching Chou
{"title":"On the variability of threshold voltage window in gate-injection versatile memories with Sub-60mV/dec subthreshold swing and 1012-cycling endurance","authors":"Y. Chiu, Chun-Yen Chang, S. Yen, C. Fan, H. Hsu, Chun‐Hu Cheng, Po‐Chun Chen, Po-Wei Chen, G. Liou, Min-Hung Lee, Chien Liu, Wu-Ching Chou","doi":"10.1109/IRPS.2016.7574623","DOIUrl":"https://doi.org/10.1109/IRPS.2016.7574623","url":null,"abstract":"Incorporating a charge-trapped ZrSiO with ferroelectric HfZrO dielectrics, we demonstrated a gate-injection versatile memory with sub-60mV/dec subthreshold swing (SS) and large threshold voltage window (ΔVT) of >2V under a fast 20-ns speed. Moreover, it is revealed that the local defects at ZrSiO/HfZrO interface affect the ferroelectric negative capacitance tuning and thus increases the variability of VT and SS during 1012 cycling endurance.","PeriodicalId":172129,"journal":{"name":"2016 IEEE International Reliability Physics Symposium (IRPS)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133121528","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Timing characterizations of device and CPU-like circuit to ensure process reliability 器件时序特性和cpu类电路，确保工艺可靠性
2016 IEEE International Reliability Physics Symposium (IRPS) Pub Date : 2016-04-17 DOI: 10.1109/IRPS.2016.7574537
M. Hsieh, T. Yew, Y. Huang, W. Wang, N. Tseng, W. Chou, Y. Lee
{"title":"Timing characterizations of device and CPU-like circuit to ensure process reliability","authors":"M. Hsieh, T. Yew, Y. Huang, W. Wang, N. Tseng, W. Chou, Y. Lee","doi":"10.1109/IRPS.2016.7574537","DOIUrl":"https://doi.org/10.1109/IRPS.2016.7574537","url":null,"abstract":"Existing methodology and stress conditions are ideal for process benchmarking but might not be sufficient under fierce competition between advanced technology development approaches. In this paper, the importance of timing delay characterization in both device and circuit level is demonstrated and emphasized. Due to the difficulties of having accurate aging model for product level simulation during early stage of process development, silicon to simulation (S2S) correlation should be established in circuit level. Experiments in this study cover from discrete device, ring oscillator (RO) and a circuit block from ARM CPU. Based on the extensive results, the characterization of timing margin is highly recommended. So, early warnings of circuit reliability risk can be obtained to save major detours during technology development.","PeriodicalId":172129,"journal":{"name":"2016 IEEE International Reliability Physics Symposium (IRPS)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115317858","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
The complete time/temperature dependence of I-V drift in PCM devices PCM器件中I-V漂移的完全时间/温度依赖性
2016 IEEE International Reliability Physics Symposium (IRPS) Pub Date : 2016-04-17 DOI: 10.1109/IRPS.2016.7574617
M. Le Gallo, A. Sebastian, D. Krebs, M. Stanisavljevic, E. Eleftheriou
{"title":"The complete time/temperature dependence of I-V drift in PCM devices","authors":"M. Le Gallo, A. Sebastian, D. Krebs, M. Stanisavljevic, E. Eleftheriou","doi":"10.1109/IRPS.2016.7574617","DOIUrl":"https://doi.org/10.1109/IRPS.2016.7574617","url":null,"abstract":"Phase-change memory (PCM) devices are expected to play a key role in future computing systems as both memory and computing elements. Hence, a comprehensive understanding of the change in the current/voltage (I-V) characteristics of these devices with time and temperature is of considerable importance. Here, we present a unified drift model able to predict the I-V characteristics at any instance in time and at any temperature. The model was validated on large sets of experimental data for an extensive range of time (10 orders of magnitude) and temperatures (180-400 K), different phase-change materials and a collection of 4k cells from a PCM chip.","PeriodicalId":172129,"journal":{"name":"2016 IEEE International Reliability Physics Symposium (IRPS)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125169850","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Product-level reliability of GaN devices GaN器件的产品级可靠性
2016 IEEE International Reliability Physics Symposium (IRPS) Pub Date : 2016-04-17 DOI: 10.1109/IRPS.2016.7574528
S. Bahl, Daniel Ruiz, Dong Seup Lee
{"title":"Product-level reliability of GaN devices","authors":"S. Bahl, Daniel Ruiz, Dong Seup Lee","doi":"10.1109/IRPS.2016.7574528","DOIUrl":"https://doi.org/10.1109/IRPS.2016.7574528","url":null,"abstract":"To enable the widespread adoption of GaN products, the industry needs to be convinced of product-level reliability. The difficulty with product-level reliability lies with the diverse range of products and use conditions, a limited ability for system-level acceleration, and the complication from non-GaN system failures. For power management applications, however, it is possible to identify fundamental switching transitions. This allows the device to be qualified in an application-relevant manner. In this paper, we explain how hard-switching can form a fundamental switching transition for power management products. We further show that the familiar double-pulse tester is a good hard-switching qualification test vehicle. The methodology is explained in the context of the existing qualification framework for silicon transistors.","PeriodicalId":172129,"journal":{"name":"2016 IEEE International Reliability Physics Symposium (IRPS)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115077922","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 64
Software-based dynamic reliability management for GPU applications 基于软件的GPU应用动态可靠性管理
2016 IEEE International Reliability Physics Symposium (IRPS) Pub Date : 2016-04-17 DOI: 10.1109/IRPS.2016.7574507
Si Li, Vilas Sridharan, S. Gurumurthi, S. Yalamanchili
{"title":"Software-based dynamic reliability management for GPU applications","authors":"Si Li, Vilas Sridharan, S. Gurumurthi, S. Yalamanchili","doi":"10.1109/IRPS.2016.7574507","DOIUrl":"https://doi.org/10.1109/IRPS.2016.7574507","url":null,"abstract":"In this paper we propose a framework for dynamic reliability management (DRM) for GPU applications based on the idea of plug-n-play software-based reliability enhancement (SRE). The approach entails first assessing the vulnerability of GPU kernels to soft errors in program visible structures. This assessment is performed on a low level intermediate program representation rather than the application source. Second, this assessment guides selective injection of code implementing SRE techniques to protect the most vulnerable data. Code injection occurs transparently at runtime using a just-in-time (JIT) compiler. Thus, reliability enhancement is selective, transparent, on-demand, and customizable. This flexible, automated software-based DRM framework can provide an adaptable, cost-effective approach to scaling reliability of large systems. We present the results of a proof of concept implementation on NVIDIA GPUs demonstrating the ability to traverse a range of performance reliability tradeoffs.","PeriodicalId":172129,"journal":{"name":"2016 IEEE International Reliability Physics Symposium (IRPS)","volume":"48 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122654261","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
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