Experimental study of supply voltage stability during ESD

Abstract

On-chip power supply integrity may be compromised during a power-on ESD event, e.g. system-level ESD. Experimental data are provided to show that the supply integrity is a function of the rail clamp gain, its speed of response to ESD, and the amount of on-chip supply decoupling capacitance. It is also demonstrated that just a few nH of package inductance can cause the on-chip supply to briefly collapse, regardless of the rail clamp response speed.