利用低功耗电路拓扑实现软错误缓解

2016 IEEE International Reliability Physics Symposium (IRPS) Pub Date : 2016-09-26 DOI:10.1109/IRPS.2016.7574640

N. Mahatme, I. Chatterjee, S. Jagannathan, N. Gaspard, T. Assis, S. Wen, R. Wong, B. Bhuva

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引用次数: 0

摘要

采用传输门逻辑实现的算术电路的Alpha粒子实验结果表明，与标准CMOS电路相比，软错误率降低35%，功耗降低30%。分析模型证实了实验趋势，并有助于优化和预测功率- ser权衡。

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Exploiting low power circuit topologies for soft error mitigation

Alpha particle experimental results for arithmetic circuits implemented using transmission gate logic are shown to have 35% lower soft error rate as well as 30% lower power consumption compared to standard CMOS circuits. Analytical models confirm the experimental trends and help optimize and predict the power-SER trade-off.

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2016 IEEE International Reliability Physics Symposium (IRPS)

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