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Proceedings of Japan International Electronic Manufacturing Technology Symposium最新文献

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Ball Grid Array (BGA): The New Standard For High I/O Surface Mount Packages 球栅阵列(BGA):高I/O表面贴装封装的新标准
Proceedings of Japan International Electronic Manufacturing Technology Symposium Pub Date : 1993-06-09 DOI: 10.1109/IEMT.1993.639328
B. Freyman, R. Marrs
{"title":"Ball Grid Array (BGA): The New Standard For High I/O Surface Mount Packages","authors":"B. Freyman, R. Marrs","doi":"10.1109/IEMT.1993.639328","DOIUrl":"https://doi.org/10.1109/IEMT.1993.639328","url":null,"abstract":"BALL GRID ARRAY (BGA) PACKAGE the package rather than as leads on the package periphery, the 1 5 mm pitch 225 BGA package occupies significantly less area on a PCB than the 0 5 mm 208 lead PQFP alternative Figure 3 shows the size advantage of BGAs over PQFPs for different lead pitches and pin counts This graph also highlights the point that a systems designer can take advantage of the area array interconnect of BGAs to achieve very high interconnect density at the motherboard level while still maintaining a relatively large soldering pitch which does not require new processes and equipment 1 0 Plr\" 1 i I","PeriodicalId":170695,"journal":{"name":"Proceedings of Japan International Electronic Manufacturing Technology Symposium","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125163343","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
High-pin-count Quad Flat Package With Thin-film Termination Resistors 带薄膜终端电阻的高引脚数四平面封装
Proceedings of Japan International Electronic Manufacturing Technology Symposium Pub Date : 1993-06-09 DOI: 10.1109/IEMT.1993.639382
S. Sasaki, T. Kishimoto
{"title":"High-pin-count Quad Flat Package With Thin-film Termination Resistors","authors":"S. Sasaki, T. Kishimoto","doi":"10.1109/IEMT.1993.639382","DOIUrl":"https://doi.org/10.1109/IEMT.1993.639382","url":null,"abstract":"This paper describes a high-pin-count quad flat package with termination resistors for high-speed and high-pin-count LSI chips. This package has 196 I/O leads with thin-film termination resistors formed around the chip mounting cavity. Termination resistors with accurate resistance values can easily be formed without trimming. This p,ackage has good electrical performance - low crosstalk noise and little waveform distortion - and it can transmit high-speed pulses up to 1.0 Gb/s (MU). This prototype package is suitable for high-speed, high-pin- count LSI chips for high-speed systems. INTRODUCI'ION","PeriodicalId":170695,"journal":{"name":"Proceedings of Japan International Electronic Manufacturing Technology Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121898870","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Fine Pitch Tab-lsi Interconnection Technology In MCM MCM中的小间距Tab-lsi互连技术
Proceedings of Japan International Electronic Manufacturing Technology Symposium Pub Date : 1993-06-09 DOI: 10.1109/IEMT.1993.639808
F. Mori, K. Kudo, K. Tsukamoto
{"title":"Fine Pitch Tab-lsi Interconnection Technology In MCM","authors":"F. Mori, K. Kudo, K. Tsukamoto","doi":"10.1109/IEMT.1993.639808","DOIUrl":"https://doi.org/10.1109/IEMT.1993.639808","url":null,"abstract":"The quest for higher processing speed of supercomputers and mainframes has made the technology for high-density packaging extremely important. The authors have developed a new technology that permits us to connect multi-pin (487 pins) ultra-fast logic LSIs on a ceramic substrate with a fine pitch of 110 μm using TAB (Tape Automated Bonding). By developing new materials, bonding process, and manufacturing facilities, the authors were able to achieve a connection pitch finer than that which conventional technology can offer. As a result, they were able to develop an ultra-fine pitch, high-density, and high reliability packaging technology that allowed them to produce high-performance computer systems","PeriodicalId":170695,"journal":{"name":"Proceedings of Japan International Electronic Manufacturing Technology Symposium","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124028246","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 1.5 Ghz-band Saw Filter Using Flip-chip-bonding Technique 一种基于倒装键合技术的1.5 ghz波段锯形滤波器
Proceedings of Japan International Electronic Manufacturing Technology Symposium Pub Date : 1993-06-09 DOI: 10.1109/IEMT.1993.639373
K. Onishi, S. Seki, Y. Taguchi, Y. Bessho, K. Eda, T. Ishida
{"title":"A 1.5 Ghz-band Saw Filter Using Flip-chip-bonding Technique","authors":"K. Onishi, S. Seki, Y. Taguchi, Y. Bessho, K. Eda, T. Ishida","doi":"10.1109/IEMT.1993.639373","DOIUrl":"https://doi.org/10.1109/IEMT.1993.639373","url":null,"abstract":"We applied a stud-bump-bonding (SBB) technique which is a kind of flip-chip-bonding (FCB) technique to a l.5GHz-band surface acoustic wave (SAW) filter. The SAW filter mounted by the SBB technique showed almost the same frequency characteristics as that mounted by a conventional wire-bonding technique at 1.5GHz. Using the SBB technique, the area of the SAW filter became 115 comparing with conventional SAW filters mounted by the wire-bonding technique and the weight became less than 1/10 by the share of the package. The SBB technique has; a lot of potential to reduce the size and weight and to realize small and high performance modules even above GHz frequencies.","PeriodicalId":170695,"journal":{"name":"Proceedings of Japan International Electronic Manufacturing Technology Symposium","volume":"355 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124484050","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Thermal Interaction In Ld Arrays Ld阵列中的热相互作用
Proceedings of Japan International Electronic Manufacturing Technology Symposium Pub Date : 1993-06-09 DOI: 10.1109/IEMT.1993.639766
T. Hayashi, K. Sate, S. Sekine
{"title":"Thermal Interaction In Ld Arrays","authors":"T. Hayashi, K. Sate, S. Sekine","doi":"10.1109/IEMT.1993.639766","DOIUrl":"https://doi.org/10.1109/IEMT.1993.639766","url":null,"abstract":"We have investigated thermal interaction in laser diode (LD) arrays with the purpose of reducing it. A 250-pn spacing between elements in LD array chip was determined by analysis of thermal dissipation in the chip to largely prevent thermal interaction. However, the thermal interaction in a mounted chip is affected by the temperature rise in the mount, To reduce this temperature rise, we propose temperature stabilizing in which the submount temperature is monitored instead of the heatsink temperature. By the new method, the interactive temperature rise is reduced to 1/3 that obtained by the conventional method.","PeriodicalId":170695,"journal":{"name":"Proceedings of Japan International Electronic Manufacturing Technology Symposium","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125679672","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Thermally Conductive Circuit Board Using Anodized Aluminum And Polymer Thick Film 采用阳极氧化铝和聚合物厚膜的导热电路板
Proceedings of Japan International Electronic Manufacturing Technology Symposium Pub Date : 1993-06-09 DOI: 10.1109/IEMT.1993.639352
K. Takeda, Y. Uematsu
{"title":"Thermally Conductive Circuit Board Using Anodized Aluminum And Polymer Thick Film","authors":"K. Takeda, Y. Uematsu","doi":"10.1109/IEMT.1993.639352","DOIUrl":"https://doi.org/10.1109/IEMT.1993.639352","url":null,"abstract":"This paper describes newly developed thermally conductive circuit board. The board consists of an anodized aluminum substrate, which is coated with electrodeposited acrylic-melamine polymer. Both anodized aluminum and electrodeposited polymer work as insulating layers between aluminum core and electrical circuitry. Polymer thick film (PTF) is adopted as circuitization in the board. This paper describes manufacturing process and evaluation results of the board from the viewpoint of both electrical and thermal reliability. Two of prototype models for power application are demonstrated in this paper.","PeriodicalId":170695,"journal":{"name":"Proceedings of Japan International Electronic Manufacturing Technology Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129256315","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Erbium-doped Fiber Amplifier 掺铒光纤放大器
Proceedings of Japan International Electronic Manufacturing Technology Symposium Pub Date : 1993-06-09 DOI: 10.1109/IEMT.1993.639815
T. Kakinuma, S. Shikii
{"title":"Erbium-doped Fiber Amplifier","authors":"T. Kakinuma, S. Shikii","doi":"10.1109/IEMT.1993.639815","DOIUrl":"https://doi.org/10.1109/IEMT.1993.639815","url":null,"abstract":"This invention relates to an Erbium doped fiber amplifier having improved operating characteristics. Parameters which determine the operating characteristics of an erbium doped fiber amplifier are the concentration of erbium in the core of a fiber; the ratio of the radius of the core of the fiber doped with erbium relative to the radius of the core of the fiber, and, the length of the fiber. It is now recognized that improved fiber amplifier performance can be obtained by varying the core-cladding refractive index difference of the fiber. The various parameters are here defined for providing an erbium doped fiber amplifier having optimum gain characteristics.","PeriodicalId":170695,"journal":{"name":"Proceedings of Japan International Electronic Manufacturing Technology Symposium","volume":"272 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131546265","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
Super Uniform Silicon Photo Diode Covering From The UV To IR Regions 覆盖从紫外到红外区域的超均匀硅光电二极管
Proceedings of Japan International Electronic Manufacturing Technology Symposium Pub Date : 1993-06-09 DOI: 10.1109/IEMT.1993.639381
Y. Fujii, H. Mori, R. Kyuushima, A. Usami, T. Wada
{"title":"Super Uniform Silicon Photo Diode Covering From The UV To IR Regions","authors":"Y. Fujii, H. Mori, R. Kyuushima, A. Usami, T. Wada","doi":"10.1109/IEMT.1993.639381","DOIUrl":"https://doi.org/10.1109/IEMT.1993.639381","url":null,"abstract":"","PeriodicalId":170695,"journal":{"name":"Proceedings of Japan International Electronic Manufacturing Technology Symposium","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134426566","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Plasma Enhanced Cvd Method For Simultaneous Deposition On Both Sides Of The Substrate And Lts Application To The In-line Multilayer Deposition System 在衬底两侧同时沉积的等离子体增强Cvd方法及其在在线多层沉积系统中的应用
Proceedings of Japan International Electronic Manufacturing Technology Symposium Pub Date : 1993-06-09 DOI: 10.1109/IEMT.1993.639285
Y. Kokaku, H. Inaba, H. Kataoka, K. Abe, M. Sunagawa
{"title":"Plasma Enhanced Cvd Method For Simultaneous Deposition On Both Sides Of The Substrate And Lts Application To The In-line Multilayer Deposition System","authors":"Y. Kokaku, H. Inaba, H. Kataoka, K. Abe, M. Sunagawa","doi":"10.1109/IEMT.1993.639285","DOIUrl":"https://doi.org/10.1109/IEMT.1993.639285","url":null,"abstract":"","PeriodicalId":170695,"journal":{"name":"Proceedings of Japan International Electronic Manufacturing Technology Symposium","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129696727","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Air Cooling Of Mcms Mounted On Card-on- Board Packaging Systems 安装在板载包装系统上的Mcms的空气冷却
Proceedings of Japan International Electronic Manufacturing Technology Symposium Pub Date : 1993-06-09 DOI: 10.1109/IEMT.1993.639761
A. Harada, Y. Kaneko, T. Kishimoto
{"title":"Air Cooling Of Mcms Mounted On Card-on- Board Packaging Systems","authors":"A. Harada, Y. Kaneko, T. Kishimoto","doi":"10.1109/IEMT.1993.639761","DOIUrl":"https://doi.org/10.1109/IEMT.1993.639761","url":null,"abstract":"A b s t r m This paper discusses the air cooling characteristics of telecommunications multichip modules (MCMs) mounted on a card-on-board (COB) system. The main issues are to achieve a suitable baffle plate height and an optimum air flow system. We also examined the cooling performance under fan failures. A flow control guide structure provides a minimum thermal resistance of 6.5-7.6\"CMI. Allowable power dissipation per MCM is 95-110 W at an allowable temperature rise of 45°C.","PeriodicalId":170695,"journal":{"name":"Proceedings of Japan International Electronic Manufacturing Technology Symposium","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129828773","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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