Proceedings of Japan International Electronic Manufacturing Technology Symposium最新文献

{"title":"Water-based Copper Oxide Compositions For Microcircuit Applications","authors":"C. Wang, Y. Yokotani, T. Ogawa","doi":"10.1109/IEMT.1993.639752","DOIUrl":"https://doi.org/10.1109/IEMT.1993.639752","url":null,"abstract":"For purposes of environmental protection, it is desirable to use water as a solvent to replace organics in electronic materials, Copper oxide compositions and hybrid circuit fabrication processes were developed. These pastes exhibited substantial organic content reduction, while preserving the characteristics of a typical organic-based copper paste. The rapid water evaporation problem of water-based pastes was resolved by providing ionic bonding to attract water while maintaining a stable paste dispersion and rheology. The screen life of this paste under specific temperaturehumidity conditions is reported. Test circuit made from the composition exhibited a resistivity of 2.5-3.0 mW/square/l5 mm. SEM micrographs also showed a dense microstructure similar to that of a copper film made from an organic-based paste.","PeriodicalId":170695,"journal":{"name":"Proceedings of Japan International Electronic Manufacturing Technology Symposium","volume":"181 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114531766","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Multichip Module For 156mb/s Optical Interface","authors":"H. Tanaka, R. Nagaoka, T. Makabe, F. Yoshimura, Y. Kobayashi, T. Tanura, Y. Suzuki, F. Suzuki","doi":"10.1109/IEMT.1993.639358","DOIUrl":"https://doi.org/10.1109/IEMT.1993.639358","url":null,"abstract":"","PeriodicalId":170695,"journal":{"name":"Proceedings of Japan International Electronic Manufacturing Technology Symposium","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124031557","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"I/O Pin Solder Point Inspection System","authors":"T. Koezuka, Yoshinori Suto, M. Ando","doi":"10.1109/IEMT.1993.639760","DOIUrl":"https://doi.org/10.1109/IEMT.1993.639760","url":null,"abstract":"We have developed an automated inspection system that features perpendicular and variable-intensity lighting for image c o n a t enhancement and improved sensing accuracy a high-resolution camera with reflection-adaptive b i n d t i o n for improved image processing, and an adaptive inspection algorithm that modifies its defect definition criteria according to target position quickly, accurately, and reliably inspect highly dense arrays of perpendicular I/O pins soldered onto a ceramic printed wiring board (PWB). The system's Mega-Scope, a highresolution, eight-bit gray-scale CCD camera, images a 2048x2048-pixel area with a 10 pm resolution in 4 seconds, taking 60 U0 pin images at a time. The total time to inspect the position and solder fillet condition of more than eight thousand U0 pins is just U) minutes.","PeriodicalId":170695,"journal":{"name":"Proceedings of Japan International Electronic Manufacturing Technology Symposium","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122877655","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Surface Deftct Inspection For Small Sizes Of Chip- Electronic-Parts Applying Color lmage Analysis Techniques","authors":"K. Tanigichi, S. Nagata, Xu Xiaolin, T. Uno, H. Yamamoto, T. Seki, S. Kawabata, N. Yamana","doi":"10.1109/IEMT.1993.639775","DOIUrl":"https://doi.org/10.1109/IEMT.1993.639775","url":null,"abstract":"","PeriodicalId":170695,"journal":{"name":"Proceedings of Japan International Electronic Manufacturing Technology Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129450271","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Numerical Calculation Of Ground-plane Impedance In Multilayer Printed Circuit Boards","authors":"K. Sakakibara, T. Mikazuki","doi":"10.1109/IEMT.1993.639799","DOIUrl":"https://doi.org/10.1109/IEMT.1993.639799","url":null,"abstract":"As circuit speed and density increase, the design of ground planes and the placement of bypass capacitors in multilayer printed circuit boards becomes increasingly difficult because the noise due to simultaneous switching activity and electromagnetic coupling becomes a key factor in system performance. Although the plane impedance effect, which is important in estimating the noise, can often be incorporated into equivalent circuit models for use in circuit simulations, there is usually no easy way to determine what parameter values to use for accurate prediction of the behavior of a proposed ground plane 111, [2]. To calculate the ground impedance, numerical techniques such as the moment method and the finite element method must be used. For large ground planes, however, these numerical techniques cannot be used because of the required computation time [ 31. We have recently tried dividing the ground planes into small cells which size is determined by the moment method, and representing them as lumped element networks, consisting of inductors, capacitors, and resistances. The ground plane impedances can be analyzed with a general-purpose network analysis program by connecting lumped element network with each other.","PeriodicalId":170695,"journal":{"name":"Proceedings of Japan International Electronic Manufacturing Technology Symposium","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121037741","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Comparaitve Economic Analysis Of Mcm-d Fabrication Costs","authors":"P. Garrout, R. Heistand, D. Frye, J. Carr, D. Burdcaux","doi":"10.1109/IEMT.1993.639735","DOIUrl":"https://doi.org/10.1109/IEMT.1993.639735","url":null,"abstract":"","PeriodicalId":170695,"journal":{"name":"Proceedings of Japan International Electronic Manufacturing Technology Symposium","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126587146","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Development Of \"The Maple Method\"","authors":"K. Endoh, K. Nozawa, N. Hsahimoto","doi":"10.1109/IEMT.1993.639748","DOIUrl":"https://doi.org/10.1109/IEMT.1993.639748","url":null,"abstract":"1 . I N T R O D U C T I O N Recently TAB(Tape Automated Bonding)has become t h e main d r i v e r I C Assembly method f o r LCD(Liquid Crystal Disp1ay)modules. The reasons f o r t h e f i n e r p i tches a r e derived from technica l reasons corresponding t o c h a r a c t e r i s t ics of a p p l i c a t i o n s and lower c o s t . There are many s i z e s of LCD (Liquid Clystal Display) modules, from 0.7 inches f o r e l e c t r o n i c view f i n d e r s (EVF) t o 15 inches f o r workstat ions. Techniques of in te rconnec t ions f o r t h e s e panels have two c h a r a c t e r i s t i c s . The f i r s t i s a high dens i ty as t h e r e a r e up t o a million pixels on a panel , with each pixel needing a d r i v e r . The second i s a t h i n n e r and smaller cons t ruc t ion . So, COG technology has been developed using t h e technique of d i r e c t bonding d r i v e r ICs on panel g l a s s . The COG technology panel is not only have higher dens i ty and a t h i n n e r and smaller s i z e , but a l s o have f e w e r processes and !ower c o s t s as compared with t h e TAB (Tape Automated Bonding) technology. The former COG method of using conductive p a r t i c l e s with adhesives requi res severa l alignment processes , which made i t unsui table f o r mass prduct ion. We have inves t iga ted a new COG technology t h a t wi l l become a prospect ive winner of t h e next age. The above new COG technology must be able t o increase t h e number of I C e l e c t r o d e s , and t o decrease t h e s i z e of t h e LCD module and its c o s t . In a d d i t i o n , process of t h e above new COG technology must be simple. Some of t h e usual COG techniques needed severa l alignment processes f o r s e t t i n g of adhesives , and I C s . Also some of t h e usual COG s t r u c t u r e s were not small enough, and had some problems. We have developed t h e new COG technology cal led \"MAPLE\"(M1M Active Panel LSI mount Engineering) method. The MAPLE method i s a face-down bonding method t h a t bonds t h e d r i v e r I C s d i r e c t l y t o a panel g lass s u b s t r a t e using ACF (Anisotropic Conductive Film) which i s a thermoset t ing adhesive. In t h e MAPLEmethod, d r i v e r I C ch ips have s t r a i g h t Au bumps. Conductive p a r t i c l e s in t h e ACF a r e uniformly placed on t h e adhesive. \"MAPLE\" has only one alignment process. Using non-stationary heat t r a n s f e r ana lys i s and s t r e s s a n a l y s i s , w e ge t t h e most s u i t a b l e dynamics design and adhesive. Besides, t h e MAPLE method, rea l ized a very small f r i n g e s i z e and a t h i n , and highly r e l i a b i l e LCD module. The MAPLE method i s now being m a s s produced. 2 . A D V A N T A G E O F C O G The COG technology, which we have named t h e MAPLE method, needs t o interconnect with I C s and a panel g l a s s , which are both hard m a t e r i a l s , and need t o be highly r e l i a b i l e . The COG technology will not be used f o r","PeriodicalId":170695,"journal":{"name":"Proceedings of Japan International Electronic Manufacturing Technology Symposium","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116121045","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Fine Pitch And High Lead Count Multilayer Ceramic Qfp","authors":"Y. Nakatsuka, T. Yamamoto, Y. Morita, M. Fujii, H. Ohtani, E. Takahashi","doi":"10.1109/IEMT.1993.639744","DOIUrl":"https://doi.org/10.1109/IEMT.1993.639744","url":null,"abstract":"","PeriodicalId":170695,"journal":{"name":"Proceedings of Japan International Electronic Manufacturing Technology Symposium","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114987919","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Automation Of Memory Failure Analysis By Combining An Expert System With A Memory Tester/analyzer","authors":"H. Hamada, T. Tsujide, Tosiyasu Hisii","doi":"10.1109/IEMT.1993.639771","DOIUrl":"https://doi.org/10.1109/IEMT.1993.639771","url":null,"abstract":"This paper presents a methodology by which predictions of memory failure are made prior to manufacturing. Based on these predictions and supporting historical data, expert rules are automatically created and used in conjunction with a memory tester/analyzer to determine the underlying physical causes of particular memory device failures. The histogram of the failure causes for a given lot can then be plotted and evaluated. Examples of the appIication of this methodology 10 the manufacture of 4 Mbit DRAMS are given.","PeriodicalId":170695,"journal":{"name":"Proceedings of Japan International Electronic Manufacturing Technology Symposium","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123895918","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"On Chip Digital Output Semiconductor Sensor Employing Cmos Inverter Array","authors":"A. Kasamatsu, B. Kim, K. Shono","doi":"10.1109/IEMT.1993.639763","DOIUrl":"https://doi.org/10.1109/IEMT.1993.639763","url":null,"abstract":"Completely complementary operation of PMOS pull-up and NMOS pull-down of CMOS inverter array is proposed in the study for digitalizing the sensor analog signal on an Si chip. CMOS load acts as the semiconductor sensor device, whose output is connected with CMOS inverter array. The channel width of PMOS pullu p composing the CMOS inverters are regularly shifted to change the logical threshold of each CMOS inverter. The input to the CMOS inverter array is directly divided into digital codes. When surrounding temperature changes from 20'C to 100°C, both of the channel conductance and the threshold voltage of PMOS and NMOS decrease about 30%. However, the logical threshold of a CMOS inverter keeps constant (less than 0.2%) due to the cancellation of large temperature dependence of PMOS pull-up and NMOS pull-down. Thus, the surrounding temperature influence during the process to transfer the input sensor analog signal into the digital output codes is found effectively to be canceled in this study.","PeriodicalId":170695,"journal":{"name":"Proceedings of Japan International Electronic Manufacturing Technology Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122483777","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}