On Chip Digital Output Semiconductor Sensor Employing Cmos Inverter Array

Abstract

Completely complementary operation of PMOS pull-up and NMOS pull-down of CMOS inverter array is proposed in the study for digitalizing the sensor analog signal on an Si chip. CMOS load acts as the semiconductor sensor device, whose output is connected with CMOS inverter array. The channel width of PMOS pullu p composing the CMOS inverters are regularly shifted to change the logical threshold of each CMOS inverter. The input to the CMOS inverter array is directly divided into digital codes. When surrounding temperature changes from 20'C to 100°C, both of the channel conductance and the threshold voltage of PMOS and NMOS decrease about 30%. However, the logical threshold of a CMOS inverter keeps constant (less than 0.2%) due to the cancellation of large temperature dependence of PMOS pull-up and NMOS pull-down. Thus, the surrounding temperature influence during the process to transfer the input sensor analog signal into the digital output codes is found effectively to be canceled in this study.