{"title":"通过将专家系统与内存测试/分析仪相结合实现内存故障分析的自动化","authors":"H. Hamada, T. Tsujide, Tosiyasu Hisii","doi":"10.1109/IEMT.1993.639771","DOIUrl":null,"url":null,"abstract":"This paper presents a methodology by which predictions of memory failure are made prior to manufacturing. Based on these predictions and supporting historical data, expert rules are automatically created and used in conjunction with a memory tester/analyzer to determine the underlying physical causes of particular memory device failures. The histogram of the failure causes for a given lot can then be plotted and evaluated. Examples of the appIication of this methodology 10 the manufacture of 4 Mbit DRAMS are given.","PeriodicalId":170695,"journal":{"name":"Proceedings of Japan International Electronic Manufacturing Technology Symposium","volume":"10 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1993-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Automation Of Memory Failure Analysis By Combining An Expert System With A Memory Tester/analyzer\",\"authors\":\"H. Hamada, T. Tsujide, Tosiyasu Hisii\",\"doi\":\"10.1109/IEMT.1993.639771\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a methodology by which predictions of memory failure are made prior to manufacturing. Based on these predictions and supporting historical data, expert rules are automatically created and used in conjunction with a memory tester/analyzer to determine the underlying physical causes of particular memory device failures. The histogram of the failure causes for a given lot can then be plotted and evaluated. Examples of the appIication of this methodology 10 the manufacture of 4 Mbit DRAMS are given.\",\"PeriodicalId\":170695,\"journal\":{\"name\":\"Proceedings of Japan International Electronic Manufacturing Technology Symposium\",\"volume\":\"10 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1993-06-09\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of Japan International Electronic Manufacturing Technology Symposium\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEMT.1993.639771\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of Japan International Electronic Manufacturing Technology Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEMT.1993.639771","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Automation Of Memory Failure Analysis By Combining An Expert System With A Memory Tester/analyzer
This paper presents a methodology by which predictions of memory failure are made prior to manufacturing. Based on these predictions and supporting historical data, expert rules are automatically created and used in conjunction with a memory tester/analyzer to determine the underlying physical causes of particular memory device failures. The histogram of the failure causes for a given lot can then be plotted and evaluated. Examples of the appIication of this methodology 10 the manufacture of 4 Mbit DRAMS are given.