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ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)最新文献

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A 40nm 5.6TOPS/W 239GOPS/mm2 Self-Attention Processor with Sign Random Projection-based Approximation 基于符号随机投影近似的40nm 5.6TOPS/W 239GOPS/mm2自注意处理器
ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2022-09-19 DOI: 10.1109/ESSCIRC55480.2022.9911343
Seong Hoon Seo, Soo-Uck Kim, Sungjun Jung, S. Kwon, Hyunseung Lee, Jae W. Lee
{"title":"A 40nm 5.6TOPS/W 239GOPS/mm2 Self-Attention Processor with Sign Random Projection-based Approximation","authors":"Seong Hoon Seo, Soo-Uck Kim, Sungjun Jung, S. Kwon, Hyunseung Lee, Jae W. Lee","doi":"10.1109/ESSCIRC55480.2022.9911343","DOIUrl":"https://doi.org/10.1109/ESSCIRC55480.2022.9911343","url":null,"abstract":"Transformer architecture is one of the most remarkable recent breakthroughs in neural networks, achieving state-of-the-art (SOTA) performance on various natural language processing (NLP) and computer vision tasks. Self-attention is the key enabling operation for transformer-based models. However, its quadratic computational complexity to the sequence length makes this operation the major performance bottleneck for those models. Thus, we propose a novel self-attention accelerator that skips most of the computation by utilizing an approximate candidate selection algorithm. Implemented in a 40nm CMOS technology, our 5.64 mm2 chip operates at 100–600 MHz consuming 48.3-685 mW to achieve the energy and area efficiency of 0.354-5.61 TOPS/W and 239 GOPS/mm2, respectively.","PeriodicalId":168466,"journal":{"name":"ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129083362","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Wide-input-range 918MHz RF Energy Harvesting IC with Adaptive Load and Input Power Tracking Technique 具有自适应负载和输入功率跟踪技术的宽输入范围918MHz射频能量采集集成电路
ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2022-09-19 DOI: 10.1109/ESSCIRC55480.2022.9911490
Jing-Ren Yan, Hao-Yi Kuo, Y. Liao
{"title":"A Wide-input-range 918MHz RF Energy Harvesting IC with Adaptive Load and Input Power Tracking Technique","authors":"Jing-Ren Yan, Hao-Yi Kuo, Y. Liao","doi":"10.1109/ESSCIRC55480.2022.9911490","DOIUrl":"https://doi.org/10.1109/ESSCIRC55480.2022.9911490","url":null,"abstract":"This paper presents a high-efficiency radio frequency (RF) power harvesting IC with an extended input range. The proposed system comprises a reconfigurable rectifier, maximum power point tracking unit, load modulation circuit, and low-dropout regulator. The reconfigurable rectifier extends the high-efficiency range of the RF input power through stage number control and load modulation according to input power and load requirements. The design is fabricated using $0.18-mu mathrm{m}$ CMOS technology, and the chip area is $1.15 times 0.57text{mm}^{2}$. The proposed system can achieve an RF-DC power conversion efficiency greater than 20% in a 16.5-dB input power range with a peak value of 45%, and sensitivity of -16 dBm for a 1-V output voltage.","PeriodicalId":168466,"journal":{"name":"ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115500627","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
SIF-NPU: A 28nm 3.48 TOPS/W 0.25 TOPS/mm2 CNN Accelerator with Spatially Independent Fusion for Real-Time UHD Super-Resolution SIF-NPU:一个28纳米3.48 TOPS/W 0.25 TOPS/mm2 CNN加速器，具有空间独立融合，用于实时超高清超分辨率
ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2022-09-19 DOI: 10.1109/ESSCIRC55480.2022.9911509
Sumin Lee, K. Lee, Sunghwan Joo, Hong Keun Ahn, Junghyup Lee, Dohyung Kim, Bumsub Ham, Seong-ook Jung
{"title":"SIF-NPU: A 28nm 3.48 TOPS/W 0.25 TOPS/mm2 CNN Accelerator with Spatially Independent Fusion for Real-Time UHD Super-Resolution","authors":"Sumin Lee, K. Lee, Sunghwan Joo, Hong Keun Ahn, Junghyup Lee, Dohyung Kim, Bumsub Ham, Seong-ook Jung","doi":"10.1109/ESSCIRC55480.2022.9911509","DOIUrl":"https://doi.org/10.1109/ESSCIRC55480.2022.9911509","url":null,"abstract":"This paper proposes a convolutional neural network (CNN)-based super-resolution accelerator for up-scaling to ultra-HD (UHD) resolution in real-time in edge devices. A novel error-compensated bit quantization is adopted to reduce bit depth in the SR task. Spatially independent layer fusion is exploited to satisfy high throughput requirements at UHD resolution by increasing parallelism. Burst operation with write mask in the dual-port SRAM increases the process element utilization by allowing the concurrent multi-access without exploiting additional memory. The accelerator is implemented in the 28nm technology and shows at least 4.3 times higher $text{FoM}(text{TOPS}/text{mm}^{2}times text{TOPS/W)}$ of 0.87 than the state-of-art CNN accelerators. The implemented accelerator supports up-scaling up to 96 frames-per-seconds in UHD resolution.","PeriodicalId":168466,"journal":{"name":"ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126838444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 2.5 GHz 104 mW 57.35 dBc SFDR Non-linear DAC-based Direct-Digital Frequency Synthesizer in 65 nm CMOS Process 基于2.5 GHz 104 mW 57.35 dBc SFDR的65 nm CMOS工艺非线性dac直接数字频率合成器
ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2022-09-19 DOI: 10.1109/ESSCIRC55480.2022.9911334
Dong-Hyun Yoon, K. Baek, T. T. Kim
{"title":"A 2.5 GHz 104 mW 57.35 dBc SFDR Non-linear DAC-based Direct-Digital Frequency Synthesizer in 65 nm CMOS Process","authors":"Dong-Hyun Yoon, K. Baek, T. T. Kim","doi":"10.1109/ESSCIRC55480.2022.9911334","DOIUrl":"https://doi.org/10.1109/ESSCIRC55480.2022.9911334","url":null,"abstract":"This paper presents a direct-digital frequency synthesizer (DDS) with dynamic performance enhancement techniques. First, a fixed-weight decoder with an auxiliary DAC is proposed to remove the truncation spur of the phase accumulator. Second, the proposed tri-state decoding scheme reduces the number of current sources for reducing timing mismatches and capacitances. Finally, a fine current source reusing technique is developed to reduce the number of current sources and power consumption. The proposed DDS is fabricated in 65 nm CMOS technology. The worst SFDR is 57.35 dBc at 2.5 GHz with power consumption of 104 mW. The measured figure of merit is 18,124 GHz.2(SFDR/6)/W.","PeriodicalId":168466,"journal":{"name":"ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125114353","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Pipeline ADC with Negative C-assisted SC Amplifier Canceling Gain Error and Nonlinearity 一种带负c辅助SC放大器的管道ADC，可消除增益误差和非线性
ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2022-09-19 DOI: 10.1109/ESSCIRC55480.2022.9911468
Woojin Jang, Gyeong-Gu Kang, Yong Lim, Hyunsik Kim
{"title":"A Pipeline ADC with Negative C-assisted SC Amplifier Canceling Gain Error and Nonlinearity","authors":"Woojin Jang, Gyeong-Gu Kang, Yong Lim, Hyunsik Kim","doi":"10.1109/ESSCIRC55480.2022.9911468","DOIUrl":"https://doi.org/10.1109/ESSCIRC55480.2022.9911468","url":null,"abstract":"A 12-b pipeline ADC based on a new negative $boldsymbol{C}$ - assisted MDAC is presented. Proposed negative $boldsymbol{C}$ scheme aids to cancel gain error and nonlinearity by generating negative charges at the summing node during the amplification phase. A design strategy for ensuring stability even when the negative $boldsymbol{C}$ coexists is also introduced in this work. In addition, a highly $boldsymbol{G}_{mathbf{m}}$-linearized low-gain amplifier is proposed for negative $boldsymbol{C}$ implementation. The prototype ADC fabricated in a 28nm CMOS achieves 54.7dB SNDR and 71.8dB SFDR without any calibration at 320MS/s, demonstrating that the proposed scheme improves SFDR by +32dB across the Nyquist band.","PeriodicalId":168466,"journal":{"name":"ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124387527","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 2.74pJ/conversion 0.0018mm2 Temperature Sensor with On-chip Gain and Offset Correction 2.74pJ/转换0.0018mm2温度传感器片上增益和偏移校正
ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2022-09-19 DOI: 10.1109/ESSCIRC55480.2022.9911364
Yuting Shen, Mariska van der Struijk, Kevin Pelzers, Hanyue Li, E. Cantatore, P. Harpe
{"title":"A 2.74pJ/conversion 0.0018mm2 Temperature Sensor with On-chip Gain and Offset Correction","authors":"Yuting Shen, Mariska van der Struijk, Kevin Pelzers, Hanyue Li, E. Cantatore, P. Harpe","doi":"10.1109/ESSCIRC55480.2022.9911364","DOIUrl":"https://doi.org/10.1109/ESSCIRC55480.2022.9911364","url":null,"abstract":"This paper presents a dynamic temperature sensor in 65nm CMOS with on-chip analog gain and offset correction for low power systems. By shifting the reset phase of the N-bit ADC, offset correction with a range of $pm 2^{(N-1)}$ LSB is realized. Fine tuning capacitors are introduced to improve the offset correction accuracy to 0.5LSB. By adding programmable parasitic capacitors, gain errors up to 6.3% can be compensated. Thanks to the proposed analog correction techniques, the gain errors are reduced to 0.73% and the offsets are reduced to 0.5LSB. This sensor consumes 2.74pJ per conversion and only occupies an area of 0.0018 mm2 including the extra correction techniques. It has an RMS resolution of 0.47K, leading to a FoM of 0.6 pJ.K2.","PeriodicalId":168466,"journal":{"name":"ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)","volume":"272 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124397020","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Capacitance-Based Voltage Regulation- and Reference-Free Temperature-to-Digital Converter down to 0.3 V and 2.5 nW for Direct Harvesting 基于电容的电压调节和无参考的温度-数字转换器，低至0.3 V和2.5 nW，用于直接采集
ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2022-09-19 DOI: 10.1109/ESSCIRC55480.2022.9911378
O. Aiello, M. Alioto
{"title":"Capacitance-Based Voltage Regulation- and Reference-Free Temperature-to-Digital Converter down to 0.3 V and 2.5 nW for Direct Harvesting","authors":"O. Aiello, M. Alioto","doi":"10.1109/ESSCIRC55480.2022.9911378","DOIUrl":"https://doi.org/10.1109/ESSCIRC55480.2022.9911378","url":null,"abstract":"A temperature-to-digital converter for direct harvesting is proposed, where no DC-DC conversion is required between the DC harvester and the system. Temperature-induced capacitance differences are read out through ring oscillator frequency. PVT variations are suppressed by the differential nature of the temperature sensor architecture, whereas mismatch is compensated via a self-referenced calibration procedure. No reference, regulator, digital post-processing and digital direct temperature readout is needed to retain true-nW and low-$V_{min}$ operation. A 180-nm testchip tested across corner wafers shows 7bit ENOB, 2.5-4.5nW from solar and thermal direct harvesting at 0.3-0.5 V, as representative of a very wide range of environmental conditions.","PeriodicalId":168466,"journal":{"name":"ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123512539","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Interplay between charge trapping and polarization switching in MFDM stacks evidenced by frequency-dependent measurements 频率相关测量证明了MFDM堆叠中电荷俘获和极化开关之间的相互作用
ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2022-09-19 DOI: 10.1109/ESSCIRC55480.2022.9911485
J. Barbot, J. Coignus, N. Vaxelaire, C. Carabasse, Olivier Glorieux, M. Bedjaoui, F. Aussenac, F. Andrieu, F. Triozon, L. Grenouillet
{"title":"Interplay between charge trapping and polarization switching in MFDM stacks evidenced by frequency-dependent measurements","authors":"J. Barbot, J. Coignus, N. Vaxelaire, C. Carabasse, Olivier Glorieux, M. Bedjaoui, F. Aussenac, F. Andrieu, F. Triozon, L. Grenouillet","doi":"10.1109/ESSCIRC55480.2022.9911485","DOIUrl":"https://doi.org/10.1109/ESSCIRC55480.2022.9911485","url":null,"abstract":"Experimental analysis of polarization switching in metal-ferroelectric- metal and metal- ferroelectric-dielectric-metal junctions is reported. Combined GIXRD and electrical analyses demonstrate that insertion of $mathrm{A}1_{2}mathrm{O}_{3}$ dielectric layer boosts the ferroelectric polarization. Ferroelectric switching measurements at various frequencies show that the injection and trapping of charges into the ferroelectric-dielectric stack have a large influence on the polarization switching.","PeriodicalId":168466,"journal":{"name":"ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)","volume":"204 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121904774","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Input Nonlinear Adaptive Voltage Position Technique in the Switched-capacitor Converter with Feedforward Compensation for 87.8% Peak Efficiency under 8X Input Interference 8X输入干扰下具有前馈补偿的开关电容变换器的输入非线性自适应电压位置技术，峰值效率为87.8%
ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2022-09-19 DOI: 10.1109/ESSCIRC55480.2022.9911306
Shu-Yung Lin, Sheng Cheng Lee, Ke-Horng Chen, Kuo-Lin Zheng, Ying-Hsi Lin, Shian-Ru Lin, Tsung-Yen Tsai
{"title":"Input Nonlinear Adaptive Voltage Position Technique in the Switched-capacitor Converter with Feedforward Compensation for 87.8% Peak Efficiency under 8X Input Interference","authors":"Shu-Yung Lin, Sheng Cheng Lee, Ke-Horng Chen, Kuo-Lin Zheng, Ying-Hsi Lin, Shian-Ru Lin, Tsung-Yen Tsai","doi":"10.1109/ESSCIRC55480.2022.9911306","DOIUrl":"https://doi.org/10.1109/ESSCIRC55480.2022.9911306","url":null,"abstract":"The proposed switched capacitor converter for energy harvesting applications can have a wide input range of 0.25V to 2V.The input nonlinear adaptive voltage position (INAVP) control and feedforward compensation can decrease ΔVoutand the settling time in line transients. The mismatch calibration circuit can reduce the influence caused by the mismatch in different phase. The highest peak efficiency is 87.8%. The reduced efficiency variation is 11.6% in the case of 800% Vin perturbation.","PeriodicalId":168466,"journal":{"name":"ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)","volume":"373 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122164127","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Frequency modulation of conductance level in PCM device for neuromorphic applications 用于神经形态应用的PCM器件电导电平的频率调制
ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2022-09-19 DOI: 10.1109/ESSCIRC55480.2022.9911461
A. Trabelsi, C. Cagli, T. Hirtzlin, O. Cueto, M. Cyrille, E. Vianello, V. Meli, V. Sousa, G. Bourgeois, F. Andrieu
{"title":"Frequency modulation of conductance level in PCM device for neuromorphic applications","authors":"A. Trabelsi, C. Cagli, T. Hirtzlin, O. Cueto, M. Cyrille, E. Vianello, V. Meli, V. Sousa, G. Bourgeois, F. Andrieu","doi":"10.1109/ESSCIRC55480.2022.9911461","DOIUrl":"https://doi.org/10.1109/ESSCIRC55480.2022.9911461","url":null,"abstract":"In this study we report for the first time the control of conductance level in PCM cells by means of a frequency modulation of progressive SET pulses. We show that by applying a train of progressive SET pulses, the conductance increases gradually and eventually saturates to a value Gsat. The latter can be tailored by changing the duty cycle of the pulse train. We propose a simple physics-based model to explain this effect. First, we simulated the thermal condition in the active region and showed that the increase of conductance was due to nucleation of a spherical hollow region around a central core, where re-amorphization takes place during programming. Based on this we illustrate that the frequency modulation can be analytically described by an equilibrium equation where the increase of conductance is balanced by the intrinsic chalcogenide resistance drift. The model is in very good agreement with data and shows that a fine tuning of the PCM device can be achieved. A frequency blind modulation of the programming pulse is believed to be much easier to be implemented in neuromorphic circuits as synaptic device [1] [2].","PeriodicalId":168466,"journal":{"name":"ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128376196","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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