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ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)最新文献

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Non-Volatile Ternary Content Addressable Memory based on Phase Change Nanoelectromechanical (NEM) Relay 基于相变纳米机电(NEM)继电器的非易失性三元内容可寻址存储器
ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2022-09-19 DOI: 10.1109/ESSCIRC55480.2022.9911327
Mohammad Ayaz Masud, Luis Hurtado, G. Piazza
{"title":"Non-Volatile Ternary Content Addressable Memory based on Phase Change Nanoelectromechanical (NEM) Relay","authors":"Mohammad Ayaz Masud, Luis Hurtado, G. Piazza","doi":"10.1109/ESSCIRC55480.2022.9911327","DOIUrl":"https://doi.org/10.1109/ESSCIRC55480.2022.9911327","url":null,"abstract":"We demonstrate, for the first time, a ternary content-addressable memory (TCAM) architecture based on phase change nanoelectromechanical relays (PCNRs). The non-volatility (NV), high ON-OFF ratio (108), and low leakage operation make PCNR an ideal candidate for high density TCAM. Additionally, PCNR devices are back-end-of-the-line (BEOL) compatible, allowing for a very small TCAM cell size of 18F2. A TCAM, with only 1 transistor and 2 PCNR devices (1T2P) per cell is simulated and it exhibits 133 ps search latency and 0.721 pJ energy consumption for 64 bits, making it one of the most competitive approaches for TCAM using beyond CMOS technologies.","PeriodicalId":168466,"journal":{"name":"ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129928754","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Ferroelectric Schottky Barrier MOSFET as Analog Synapses for Neuromorphic Computing 作为神经形态计算模拟突触的铁电肖特基势垒MOSFET
ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2022-09-19 DOI: 10.1109/ESSCIRC55480.2022.9911305
Feng Xi, Andreas Grenmy, Jiayuan Zhang, Yisong Han, J. Bae, D. Grützmacher, Qing-Tai Zhao
{"title":"Ferroelectric Schottky Barrier MOSFET as Analog Synapses for Neuromorphic Computing","authors":"Feng Xi, Andreas Grenmy, Jiayuan Zhang, Yisong Han, J. Bae, D. Grützmacher, Qing-Tai Zhao","doi":"10.1109/ESSCIRC55480.2022.9911305","DOIUrl":"https://doi.org/10.1109/ESSCIRC55480.2022.9911305","url":null,"abstract":"In this paper, artificial synapses based on ferroelectric Schottky barrier MOSFETs (FE-SBFETs) are presented. The FE-SBFETs are fabricated with Si doped Hf02 ferroelectric layers scaling down to a gate length of 40 nm and using single crystalline NiSi2 contacts on siliconon-insulator (SOI) substrates. The ferroelectric polarization switching dynamics gradually modulate the Schottky barriers, thus programming the device conductance by applying stimulus on the gate to imitate the short- and long-term plasticity of biological synapse, including excitatory/inhibitory postsynaptic current (EPSC/IPSC), paired-pulse facilitation (PPF) and long-term potentiation (LTP) and long-term depression (LTD) behaviors. Based on a multilayer perceptron artificial neural networks, a high recognition accuracy (83.6%) is achieved for handwritten digits. These findings demonstrate FE-SBFET has high potential as an ideal synaptic component for the future intelligent neuromorphic network.","PeriodicalId":168466,"journal":{"name":"ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121644140","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A Nonuniform Sampling Lifetime Estimation Technique for Luminescent Oxygen Measurements 一种用于发光氧测量的非均匀采样寿命估计技术
ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2022-09-19 DOI: 10.1109/ESSCIRC55480.2022.9911496
I. Costanzo, Devdip Sen, John McNeill, U. Guler
{"title":"A Nonuniform Sampling Lifetime Estimation Technique for Luminescent Oxygen Measurements","authors":"I. Costanzo, Devdip Sen, John McNeill, U. Guler","doi":"10.1109/ESSCIRC55480.2022.9911496","DOIUrl":"https://doi.org/10.1109/ESSCIRC55480.2022.9911496","url":null,"abstract":"This paper presents a nonuniform sampling technique for measuring the lifetime of luminescent materials for oxygen sensing. The system features a switched-capacitor circuit to implement fixed-voltage steps for quantization, enabling long integration times without saturating the front-end amplifier. A control circuit automatically tunes the light emitting diode (LED) excitation pulses to avoid overpowering or starving the front end as photodiode current varies with changes in the partial pressure of oxygen. Time gating of the front-end integrator removes the need for optical filtering. The analog front end (AFE) has a gain bandwidth product of 10 MHz and an input-referred noise of 124 $mu V_{rms}$ (measured 200 Hz - 100 kHz). The circuit was realized in 180 nm CMOS technology. The AFE and LED driver consume a maximum of 16 $mu J$ per calculation. We have demonstrated the entire system's functionality by measuring oxygen concentrations from 0 to 240 mmHg in a controlled gas vessel. The results indicate satisfactory linearity on a Stern-Volmer plot covering the human-relevant range of 50 to 150 mmHg.","PeriodicalId":168466,"journal":{"name":"ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122384939","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Semiconductors take the driver's seat - challenges and opportunities for the car of the future 半导体占据主导地位——未来汽车的挑战与机遇
ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2022-09-19 DOI: 10.1109/ESSCIRC55480.2022.9911388
T. Gutheit
{"title":"Semiconductors take the driver's seat - challenges and opportunities for the car of the future","authors":"T. Gutheit","doi":"10.1109/ESSCIRC55480.2022.9911388","DOIUrl":"https://doi.org/10.1109/ESSCIRC55480.2022.9911388","url":null,"abstract":"90% of the innovations in modern vehicles are enabled by semiconductors. The trend towards autonomous driving and electrification of the drive train imposes additional requirements on electronics in the vehicle which cannot be met by using semiconductor components from the consumer domains. The talk will illustrate the main challenges on semiconductor devices in automotive use cases related to computing performance, reliability, power consumption, sensor accuracy and robustness, security and functional safety for enabling the vehicle of tomorrow. We will provide an outlook on advanced semiconductor technologies and concepts which will be instrumental to tackle these challenges successfully.","PeriodicalId":168466,"journal":{"name":"ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125257199","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Reminiscing through 40 years of CMOS analog circuit design: from audio to GHz 回顾40年的CMOS模拟电路设计:从音频到GHz
ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2022-09-19 DOI: 10.1109/ESSCIRC55480.2022.9911353
R. Castello
{"title":"Reminiscing through 40 years of CMOS analog circuit design: from audio to GHz","authors":"R. Castello","doi":"10.1109/ESSCIRC55480.2022.9911353","DOIUrl":"https://doi.org/10.1109/ESSCIRC55480.2022.9911353","url":null,"abstract":"During my research life I witness 40 years of CMOS analog design. I was lucky to be at U.C. Berkeley when all this started, and my Ph.D. with Prof. Paul Gray was part of it. I kept my focus on analog CMOS at the University of Pavia even if the migration toward digital and the dream of analog design automation decreased the interest on it. CMOS circuits moved from audio to THz as the technology scaled three orders of magnitude. This talk will show this amazing evolution with some example circuit and system primarily for RF but not only. I will look from both academia and industry presenting device, circuit and architectural innovations. I hope this talk can bring motivation to younger researchers to drive the next CMOS developments.","PeriodicalId":168466,"journal":{"name":"ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133736396","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
INTIACC: A 32-bit Floating-Point Programmable Custom-ISA Accelerator for Solving Classes of Partial Differential Equations 求解偏微分方程类的32位浮点可编程自定义isa加速器
ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2022-09-19 DOI: 10.1109/ESSCIRC55480.2022.9911441
Paul Xuanyuanliang Huang, Dan Jang, Y. Tsividis, Mingoo Seok
{"title":"INTIACC: A 32-bit Floating-Point Programmable Custom-ISA Accelerator for Solving Classes of Partial Differential Equations","authors":"Paul Xuanyuanliang Huang, Dan Jang, Y. Tsividis, Mingoo Seok","doi":"10.1109/ESSCIRC55480.2022.9911441","DOIUrl":"https://doi.org/10.1109/ESSCIRC55480.2022.9911441","url":null,"abstract":"We propose a numerical integration accelerator (INTIACC) that speeds up the solution of partial differential equations (PDEs) for scientific computing. In contrast to recent works, INTIACC applies to a variety of PDEs and boundary conditions, has enhanced nonlinear function capability, supports high-order integration algorithms, and uses floating-point arithmetic for orders of magnitude smaller solution error. With all the benefits, our test chip still achieves 40X speed-up over prior accelerators and orders of magnitudes over CPU and GPU based systems.","PeriodicalId":168466,"journal":{"name":"ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122244836","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 1-to-4b 16.8-POPS/W 473-TOPS/mm2 6T-based In-Memory Computing SRAM in 22nm FD-SOI with Multi-Bit Analog Batch-Normalization 1-to-4b 16.8-POPS/W 473-TOPS/mm2 6 -based in - memory Computing SRAM, 22nm FD-SOI, Multi-Bit Analog Batch-Normalization
ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2022-09-19 DOI: 10.1109/ESSCIRC55480.2022.9911348
Adrian Kneip, M. Lefebvre, Julien Verecken, D. Bol
{"title":"A 1-to-4b 16.8-POPS/W 473-TOPS/mm2 6T-based In-Memory Computing SRAM in 22nm FD-SOI with Multi-Bit Analog Batch-Normalization","authors":"Adrian Kneip, M. Lefebvre, Julien Verecken, D. Bol","doi":"10.1109/ESSCIRC55480.2022.9911348","DOIUrl":"https://doi.org/10.1109/ESSCIRC55480.2022.9911348","url":null,"abstract":"Computing in-memory (CIM) is rapidly becoming an enticing solution to accelerate convolutional neural networks (CNNs) at the edge. Yet, low-precision current-based CIM-SRAMs face severe SNR degradation due to numerous analog non-idealities and high quantization noise when performing analog-to-digital conversion prior to digital batch-normalization (DBN). In this paper, we propose a dual-supply 1-to-4b CIM-SRAM macro in 22nm FD-SOI using 6T foundry bitcells, co-designed with a CIM-aware CNN training framework to overcome these challenges. The macro includes a multi-bit analog BN (ABN) unit combined with self-calibrating dual-phase sense-amplifiers (SCDP-SAs). Measurement results show peak 1b-normalized power and area efficiencies of 16.8POPS/W and 473TOPS/mm2at O.4/0.8V supply and 100 MHz, surpassing existing low-precision designs.","PeriodicalId":168466,"journal":{"name":"ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130372293","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Configurable Energy-Efficient Lattice-Based Post-Quantum Cryptography Processor for IoT Devices 用于物联网设备的可配置节能的基于晶格的后量子加密处理器
ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2022-09-19 DOI: 10.1109/ESSCIRC55480.2022.9911531
Byungjun Kim, Jaehan Park, Seunghyun Moon, K. Kang, J. Sim
{"title":"Configurable Energy-Efficient Lattice-Based Post-Quantum Cryptography Processor for IoT Devices","authors":"Byungjun Kim, Jaehan Park, Seunghyun Moon, K. Kang, J. Sim","doi":"10.1109/ESSCIRC55480.2022.9911531","DOIUrl":"https://doi.org/10.1109/ESSCIRC55480.2022.9911531","url":null,"abstract":"This work presents a configurable lattice-based post-quantum cryptography processor suitable for lightweight edge devices. To reduce hardware cost and energy consumption, it employs a look-up-table-based modular multiplication for the number-theoretic transform and a real-time processing for polynomial sampling. Implementation in 28nm CMOS shows 15.4x and 14.5x reductions of gate count and on-chip memory size, respectively, compared to the previous state-of-the-art implementation at the cost of only 54% in energy.","PeriodicalId":168466,"journal":{"name":"ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124036917","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Direct Sensor Readout Circuit Using VCO-Driven Chopping with 42dB SNR at 800µVpp Input 采用vco驱动斩波的直接传感器读出电路，在800 μ Vpp输入下信噪比为42dB
ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2022-09-19 DOI: 10.1109/ESSCIRC55480.2022.9911309
Yingjie Chen, M. Guzman, Beomsoo Park, N. Maghari
{"title":"A Direct Sensor Readout Circuit Using VCO-Driven Chopping with 42dB SNR at 800µVpp Input","authors":"Yingjie Chen, M. Guzman, Beomsoo Park, N. Maghari","doi":"10.1109/ESSCIRC55480.2022.9911309","DOIUrl":"https://doi.org/10.1109/ESSCIRC55480.2022.9911309","url":null,"abstract":"This work presents a new voltage-controlled-oscillator (VCO)-based sensor readout chip for sub-millivolt signal sensing applications. The proposed sensor front-end utilizes a new multi-path chopping topology driven by VCO output phases that reduces the modulation noise magnitude by spreading the noise power over a relatively large frequency range. It removes the need for extra filters required by the conventional chopping technique, reducing the front-end area and complexity. A linearization technique for the VCO is developed to improve the linear operating range. The prototype was implemented in a 65nm process. It processes an 800µVpp input signal and achieves 42dB SNR with 1KHz bandwidth while consuming 1.84µW.","PeriodicalId":168466,"journal":{"name":"ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127723770","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 24 GHz Quadrature VCO Based on Coupled PLL with -134 dBc/Hz Phase Noise at 10 MHz Offset in 28 nm CMOS 基于耦合锁相环的24ghz正交压控振荡器，相位噪声为-134 dBc/Hz，偏移量为10mhz
ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2022-09-19 DOI: 10.1109/ESSCIRC55480.2022.9911510
Agata Iesurum, Davide Manente, F. Padovan, M. Bassi, A. Bevilacqua
{"title":"A 24 GHz Quadrature VCO Based on Coupled PLL with -134 dBc/Hz Phase Noise at 10 MHz Offset in 28 nm CMOS","authors":"Agata Iesurum, Davide Manente, F. Padovan, M. Bassi, A. Bevilacqua","doi":"10.1109/ESSCIRC55480.2022.9911510","DOIUrl":"https://doi.org/10.1109/ESSCIRC55480.2022.9911510","url":null,"abstract":"This work breaks the trade-off between quadrature error and phase noise, typical of quadrature voltage-controlled oscillators (QVCOs), by leveraging a coupled PLL approach. Prototypes implemented in a 28 nm bulk CMOS technology show $0.9^{circ}$ quadrature error, and -134 dBc/Hz phase noise at 10 MHz offset from the 24 GHz carrier. The measured tuning range spans from 24 to 29.2 GHz, while the power consumption is 60 mW.","PeriodicalId":168466,"journal":{"name":"ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128984274","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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