ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)最新文献

{"title":"A 112-Gb/s Single-Ended PAM-4 Transceiver Front-End for Reach Extension in Long-Reach Link","authors":"Xiongshi Luo, Xuewei You, J. Fu, Zhenghao Li, Liping Zhong, Taiyang Fan, Zhang Qiu, Wenbo Xiao, Yong Chen, Quan Pan","doi":"10.1109/ESSCIRC55480.2022.9911452","DOIUrl":"https://doi.org/10.1109/ESSCIRC55480.2022.9911452","url":null,"abstract":"This paper presents a 112-Gb/s single-ended (SE) PAM-4 transceiver front-end for the reach-extension module in a 130 nm SiGe BiCMOS technology. The transmitter front-end is based on a differential-to-SE driver where the negative capacitance scheme is introduced to extend its bandwidth. The receiver front-end features a low-mismatch SE-to-differential (S2D) amplifier and an inductor-reuse continuous-time linear equalizer (CTLE). In the S2D, both the asymmetric reused inductor and capacitance compensation techniques are implemented to eliminate the mismatch at the pseudo-differential outputs. In the CTLE, both the inductor reuse and boosted current reuse techniques are adopted to save area, and further boost the maximum peaking frequency and equalization range. Our SE link demonstrates the highest 112-Gb/s PAM-4 data rate at a 20-dB channel loss with an energy efficiency of 1.81 pJ/bit.","PeriodicalId":168466,"journal":{"name":"ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121411787","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 24-30 GHz Broadband Doherty PA with a maximum 15.37 dBm Pavg and 14.6% PAEavg in 0.13 μm SiGe for 400 MHz BW 5G NR","authors":"Hao Gao, S. Mahani, David Seebacher, M. Bassi, G. Hueber","doi":"10.1109/ESSCIRC55480.2022.9911231","DOIUrl":"https://doi.org/10.1109/ESSCIRC55480.2022.9911231","url":null,"abstract":"This paper presents a 24–30 GHz broadband Doherty P A (DP A) in Infineon $0.13 mu mathrm{m}$ SiGe BiCMOS technology. A broadband transformer-based impedance inverter matching network (IIMN) is proposed and implemented to achieve simultaneous wide bandwidth and high efficiency within a compact size. Furthermore, a stacked PA unit cell topology is applied for power added efficiency (PAE) enhancement. In the 5G NR FR2 64-QAM modulated measurement from 24–30 GHz (5G N257 N258 bands) with 5% EVM constrain, this DPA achieves a maximum 17.24 dBm Pavg and 16.8% PAE with 100MHz BW. With 200 MHz BW, the maximum Pavg is 16.94 dBm, and $text{PAE}_{mathrm{a}mathrm{v}mathrm{g}}$ is 16.6%. With 400 MHz, the maximum Pavg is 15.37 dBm, and $text{PAE}_{mathrm{a}mathrm{v}mathrm{g}}$ is 14.6%. In 24–30 GHz (N257 N258), this PA could deliver above 12 dBm average output power (P avg), and its average PAE $(text{PAE}_{mathrm{a}mathrm{v}mathrm{g}})$ keeps higher than 10% in whole bands, all reported at critical $8 5^{circ}mathrm{C}$ condition.","PeriodicalId":168466,"journal":{"name":"ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124769440","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 12nm Agile-Designed SoC for Swarm-Based Perception with Heterogeneous IP Blocks, a Reconfigurable Memory Hierarchy, and an 800MHz Multi-Plane NoC","authors":"Tianyu Jia, Paolo Mantovani, Maico Cassel dos Santos, Davide Giri, Joseph Zuckerman, Erik Jens Loscalzo, M. Cochet, Karthik Swaminathan, Gabriele Tombesi, J. Zhang, Nandhini Chandramoorthy, J. Wellman, K. Tien, L. Carloni, Kenneth E. Shepard, D. Brooks, Gu-Yeon Wei, P. Bose","doi":"10.1109/ESSCIRC55480.2022.9911456","DOIUrl":"https://doi.org/10.1109/ESSCIRC55480.2022.9911456","url":null,"abstract":"This paper presents an agile-designed domain-specific SoC in 12nm CMOS for the emerging application domain of swarm-based perception. Featuring a heterogeneous tile-based architecture, the SoC was designed with an agile methodology using open-source processors and accelerators, interconnected by a multi-plane NoC. A reconfigurable memory hierarchy and a CS-GALS clocking scheme allow the SoC to run at a variety of performance/power operating points. Compared to a high-end FPGA, the presented SoC achieves 7 × performance and 62× efficiency gains for the target application domain.","PeriodicalId":168466,"journal":{"name":"ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125044715","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Esscirc 2022 Author Index","authors":"","doi":"10.1109/esscirc55480.2022.9911492","DOIUrl":"https://doi.org/10.1109/esscirc55480.2022.9911492","url":null,"abstract":"","PeriodicalId":168466,"journal":{"name":"ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123383424","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"From Less Batteries to Battery-Less: Enabling A Greener World through Ultra-Wide Power-Performance Adaptation down to pWs","authors":"M. Alioto","doi":"10.1109/ESSCIRC55480.2022.9911465","DOIUrl":"https://doi.org/10.1109/ESSCIRC55480.2022.9911465","url":null,"abstract":"This paper presents a holistic perspective on recent advances in silicon systems for distributed and decentralized systems (e.g., IoT, AIoT), whose count is trending towards the trillions exponentially. At such unprecedented scale, batteries impose severe scaling limitations in terms of form factor, system lifetime and uptime, sensor node cost, system cost (e.g., due to battery/sensor node replacement), and a heavy environmental impact at disposal time. Accordingly, sustained growth in the number of connected devices mandates drastic battery shrinking and ultimately elimination at scale. Beyond the straightforward reduction in the battery utilization via long sleep modes, this paper focuses on the prominent class of miniaturized (mm-scale) battery-indifferent and battery-less systems. Recent and unfolding design techniques are presented to enable purely-harvested operation, while still maintaining sensor nodes alert/available, long lived (e.g., beyond the battery shelf life), millimeter-sized and low cost. This paper and its keynote speech companion at ESSCIRC discusses how to achieve such goals through system peak power adaptation down to the nW level, rather than conventional average. Fundamental principles are demonstrated on silicon across all major sensor node sub-systems (e.g., processing, sensor interfaces, wireless communications). Overall, the design techniques described in this keynote paper aim to enable next-generation ubiquitous, low-cost, miniaturized yet alert sensor nodes for sustainable scale-up. From a technological viewpoint, the resulting advances aim to make scaling to the trillions economically and logistically sustainable. Even more importantly, they are crucially needed to make trillion-scale systems environmentally sustainable, addressing the gargantuan threat posed by trillions of batteries lying ahead, from production to disposal. Beyond the well-established notion of VLSI systems on a chip, sustainability in very large-scale (distributed/decentralized) systems really starts from design.","PeriodicalId":168466,"journal":{"name":"ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124201175","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 28nm 8-bit Floating-Point Tensor Core based CNN Training Processor with Dynamic Activation/Weight Sparsification","authors":"S. Venkataramanaiah, Jian Meng, Han-Sok Suh, Injune Yeo, Jyotishman Saikia, Sai Kiran Cherupally, Yichi Zhang, Zhiru Zhang, J.-s. Seo","doi":"10.1109/ESSCIRC55480.2022.9911359","DOIUrl":"https://doi.org/10.1109/ESSCIRC55480.2022.9911359","url":null,"abstract":"We present an 8-bit floating-point (FP8) training processor which implements (1) highly parallel tensor cores (fused multiply-add trees) that maintain high utilization throughout forward propagation (FP), backward propagation (BP), and weight update (WU) phases of the training process, (2) hardware-efficient channel gating for dynamic output activation sparsity, (3) dynamic weight sparsity based on group Lasso, and (4) gradient skipping based on FP prediction error. We develop a custom ISA to flexibly support different CNN topologies and training parameters. The 28nm prototype chip demonstrates large improvements in FLOPs reduction (7.3 ×), energy efficiency (16.4 TFLOPS/W), and overall training latency speedup (4.7×), for both supervised and self-supervised training tasks.","PeriodicalId":168466,"journal":{"name":"ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132257592","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 128ksps 120dB THD Low Noise Analog Front End","authors":"Gerard Mora-Puchalt, Gabriel Banarie, Pawel Czapor, A. Sherry, R. Maurino, Jesús Bonache, Italo Medina","doi":"10.1109/ESSCIRC55480.2022.9911425","DOIUrl":"https://doi.org/10.1109/ESSCIRC55480.2022.9911425","url":null,"abstract":"This paper describes a complete analog to digital front-end system consisting of a programmable gain two stage capacitive gain amplifier (CGA) driving a multistage delta-sigma ADC. It features a 60kHz bandwidth and 1ppm/FSR linearity at low gains ($mathrm{G}leq 8$) and 3ppm/FSR at high gains ($mathrm{G}> 8$). At a gain of 128, it achieves an input referred noise of 5.5nV/√Hz at a power consumption of 43mW.","PeriodicalId":168466,"journal":{"name":"ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128109942","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A PMUT Transceiver Front-End with 100-V TX Driver and Low-Noise Voltage Amplifier in BCD-SOI Technology","authors":"Lara Novaresi, P. Malcovati, A. Mazzanti, E. Bonizzoni, Marco Terenzi, Stefano Ottaviani, D. Ghisu, F. Quaglia, A. Savoia","doi":"10.1109/ESSCIRC55480.2022.9911390","DOIUrl":"https://doi.org/10.1109/ESSCIRC55480.2022.9911390","url":null,"abstract":"This paper presents an analog transceiver for PMUT-based portable ultrasound medical imaging probes, working in the 2–4 MHz frequency range. The transceiver, fabricated in a 160-nm BCD-SOI technology, delivers a three-level train of pulses with amplitude up to ±50 V to the ultrasound transducer and collects the back-scattered echoes with a receiver chain, consisting of a low-noise voltage amplifier with programmable gain and a buffer. The circuit, connected to a PMUT, achieves a RX sensitivity of 50 mV/kPa at minimum gain and an input-referred noise spectral density of $13,text{nV}/sqrt{Hz}$ at 2.3 MHz, consuming 5.4 mW. The peak RX sensitivity, obtained with acoustic measurements in a water tank, is 50 mV/kPa at 2.3 MHz.","PeriodicalId":168466,"journal":{"name":"ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127369767","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Quantum-Correlated Photon-Pair Source with Integrated Feedback Control in 45 nm CMOS","authors":"D. Kramnik, I. Wang, J. Cabanillas, Anirudh Ramesh, S. Buchbinder, P. Zarkos, C. Adamopoulos, Premjeet Kumar, M. Popović, V. Stojanović","doi":"10.1109/ESSCIRC55480.2022.9911513","DOIUrl":"https://doi.org/10.1109/ESSCIRC55480.2022.9911513","url":null,"abstract":"Integrated photonics provides scalability needed for useful photonic quantum information processing. Many optical resonators must be aligned to the same pump wavelength to produce sources of quantum-correlated photon pairs that drive such systems, but existing solutions rely on manual alignment or offline tuning based on external photodiodes and bulky off-chip electronics, limiting scalability. Here we demonstrate feedback control of four-wave mixing (stimulated and spontaneous) in a silicon microring using circuits integrated alongside photonics in a standard 45 nm CMOS foundry process. The carrier-sweepout-generated feedback signal enables in-situ operation in the photon-pair generation regime, which is a key building block enabling large-scale CMOS quantum-photonic systems-on-chip.","PeriodicalId":168466,"journal":{"name":"ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)","volume":"127 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123294633","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 28GHz Area-Efficient CMOS Vector-Summing Phase Shifter Utilizing Phase-Inverting Type-I Poly-Phase Filter for 5G New Radio","authors":"Minzhe Tang, Yi Zhang, Jian Pang, A. Shirane, K. Okada","doi":"10.1109/ESSCIRC55480.2022.9911339","DOIUrl":"https://doi.org/10.1109/ESSCIRC55480.2022.9911339","url":null,"abstract":"A 28GHz CMOS passive vector-summing phase shifter is demonstrated in this paper. The proposed design consists of a phase-inverting type-I poly-phase filter and a 45° switch-type phase shifter. By adopting the phase-inverting poly-phase filter for I/Q generation, I/Q weight assignment and summation, the proposed design can realize ± 22.5° phase tuning with fine resolution in each phase quadrant. Together with the 45° phase shifting provided by the switch-type phase shifter, the proposed design can achieve a 360° phase coverage in a compact area of 0.1mm2. Transformers are utilized for the inter-stage and output matching, which shrink the area compared with transmission lines. In measurement, the fabricated passive vector-summing phase shifter realizes a root mean square (RMS) phase error smaller than 1.77° from 26.5GHz to 29.5GHz and reaches 0.06° at 28GHz with the help of the fine-tuning in phase-inverting polyphase filter. The measured RMS gain error of the design is smaller than 0.27dB in the desired frequency range.","PeriodicalId":168466,"journal":{"name":"ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)","volume":"569 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122538760","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}